dspic33fj128mc706at-i-pt Microchip Technology Inc., dspic33fj128mc706at-i-pt Datasheet - Page 155

• Manufacturer Part Number: dspic33fj128mc706at-i-pt
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

10.0
The
provide the ability to manage power consumption by
selectively managing clocking to the CPU and the
peripherals. In general, a lower clock frequency and a
reduction in the number of circuits being clocked
constitutes
dsPIC33FJXXXMCX06A/X08A/X10A
manage power consumption in four different ways:
• Clock frequency
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while still maintaining critical application features, such
as timing-sensitive communications.
10.1
dsPIC33FJXXXMCX06A/X08A/X10A devices allow a
wide range of clock frequencies to be selected under
application control. If the system clock configuration is
not
high-precision oscillators by simply changing the
NOSC bits (OSCCON<10:8>). The process of
changing a system clock during operation, as well as
limitations to the process, are discussed in more detail
in Section 9.0 “Oscillator Configuration”.
EXAMPLE 10-1:
© 2009 Microchip Technology Inc.
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
Note:
locked,
dsPIC33FJXXXMCX06A/X08A/X10A
POWER-SAVING FEATURES
Clock Frequency and Clock
Switching
This data sheet summarizes the features of
the dsPIC33FJXXXMCX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 9.
“Watchdog Timer and Power-Saving
Modes” (DS70196) in the “dsPIC33F
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
users
lower
PWRSAV INSTRUCTION SYNTAX
can
dsPIC33FJXXXMCX06A/X08A/X10A
; Put the device into SLEEP mode
; Put the device into IDLE mode
choose
consumed
low-power
devices
devices
power.
can
Preliminary
or
10.2
dsPIC33FJXXXMCX06A/X08A/X10A
two special power-saving modes that are entered
through the execution of a special PWRSAV instruction.
Sleep mode stops clock operation and halts all code
execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembly syntax of the PWRSAV
instruction is shown in Example 10-1.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to “wake-up”.
10.2.1
Sleep mode has the following features:
• The system clock source is shut down. If an
• The device current consumption is reduced to a
• The Fail-Safe Clock Monitor does not operate
• The LPRC clock continues to run in Sleep mode if
• The WDT, if enabled, is automatically cleared
• Some device features or peripherals may continue
The device will wake-up from Sleep mode on any of the
following events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep, the processor restarts with the
same clock source that was active when Sleep mode
was entered.
on-chip oscillator is used, it is turned off.
minimum, provided that no I/O pin is sourcing
current.
during Sleep mode since the system clock source
is disabled.
the WDT is enabled.
prior to entering Sleep mode.
to operate in Sleep mode. This includes items such
as the input change notification on the I/O ports
and peripherals that use an external clock input.
Any peripheral that requires the system clock
source for its operation is disabled in Sleep mode.
Note:
Instruction-Based Power-Saving
Modes
SLEEP MODE
SLEEP_MODE and IDLE_MODE are con-
stants defined in the assembler include
file for the selected device.
DS70594A-page 153
devices
have