dspic33fj128mc706at-i-pt Microchip Technology Inc., dspic33fj128mc706at-i-pt Datasheet - Page 163

• Manufacturer Part Number: dspic33fj128mc706at-i-pt
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

11.0
All of the device pins (except V
OSC1/CLKIN) are shared between the peripherals and
the parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
11.1
A parallel I/O port that shares a pin with a peripheral is, in
general, subservient to the peripheral. The peripheral’s
output buffer data and control signals are provided to a
pair of multiplexers. The multiplexers select whether the
peripheral or the associated port has ownership of the
output data and control signals of the I/O pin. The logic
also prevents “loop through”, in which a port’s digital out-
put can drive the input of a peripheral that shares the
same pin. Figure 11-1 shows how ports are shared with
other peripherals and the associated I/O pin to which
they are connected.
FIGURE 11-1:
© 2009 Microchip Technology Inc.
Note:
I/O PORTS
Parallel I/O (PIO) Ports
This data sheet summarizes the features of
the dsPIC33FJXXXMCX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 10. “I/O
Ports” (DS70193) in the “dsPIC33F
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
Read TRIS
Data Bus
WR TRIS
WR LAT +
WR PORT
Read LAT
Read Port
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
dsPIC33FJXXXMCX06A/X08A/X10A
Peripheral Module
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
PIO Module
DD
TRIS Latch
Data Latch
D
D
CK
CK
, V
SS
Q
Q
, MCLR and
Preliminary
Output Multiplexers
When a peripheral is enabled and actively driving an
associated pin, the use of the pin as a general purpose
output pin is disabled. The I/O pin may be read, but the
output driver for the parallel port bit will be disabled. If
a peripheral is enabled but the peripheral is not actively
driving a pin, that pin may be driven by a port.
All port pins have three registers directly associated
with their operation as digital I/O. The Data Direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx), read the latch.
Writes to the latch, write the latch. Reads from the port
(PORTx), read the port pins, while writes to the port
pins, write the latch.
Any bit and its associated data and control registers
that are not valid for a particular device will be disabled.
That means the corresponding LATx and TRISx
registers, and the port pins will read as zeros.
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs. An example is the
INT4 pin.
1
1
0
0
Note:
Output Enable
Output Data
The voltage on a digital input pin can be
between -0.3V to 5.6V.
Input Data
I/O
I/O Pin
DS70594A-page 161