dspic33fj128mc706at-i-pt Microchip Technology Inc., dspic33fj128mc706at-i-pt Datasheet - Page 211

• Manufacturer Part Number: dspic33fj128mc706at-i-pt
• Description: High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

20.0
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in the dsPIC33FJXXXMCX06A/X08A/X10A
device family. The UART is a full-duplex, asynchronous
system that can communicate with peripheral devices,
such as personal computers, LIN/J2602, RS-232 and
RS-485 interfaces. The module also supports a hard-
ware flow control option with the UxCTS and UxRTS
pins and also includes an IrDA
The primary features of the UART module are:
• Full-Duplex, 8-Bit or 9-Bit Data Transmission
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
FIGURE 20-1:
© 2009 Microchip Technology Inc.
Note:
through the UxTX and UxRX Pins
Note 1: Both UART1 and UART2 can trigger a DMA data transfer. If U1TX, U1RX, U2TX or U2RX is selected as
2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word (i.e.,
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
This data sheet summarizes the features of
the dsPIC33FJXXXMCX06A/X08A/X10A
family of devices. However, it is not
intended to be a comprehensive reference
source. To complement the information in
this data sheet, refer to Section 17.
“UART” (DS70188) in the “dsPIC33F
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
a DMA IRQ source, a DMA transfer occurs when the U1TXIF, U1RXIF, U2TXIF or U2RXIF bit gets set as
a result of a UART1 or UART2 transmission or reception.
UTXISEL<1:0> = 00 and URXISEL<1:0> = 00).
UART SIMPLIFIED BLOCK DIAGRAM
dsPIC33FJXXXMCX06A/X08A/X10A
®
Hardware Flow Control
Baud Rate Generator
encoder and decoder.
UART Transmitter
UART Receiver
IrDA
®
Preliminary
• Hardware Flow Control Option with UxCTS and
• Fully Integrated Baud Rate Generator with 16-Bit
• Baud Rates Ranging from 1 Mbps to 15 bps at 16x
• Baud Rates Ranging from 4 Mbps to 61 bps at 4x
• 4-Deep First-In-First-Out (FIFO) Transmit Data
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-bit mode with Address Detect
• Transmit and Receive Interrupts
• A Separate Interrupt for all UART Error Conditions
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA
• 16x Baud Clock Output for IrDA
A simplified block diagram of the UART is shown in
Figure 20-1. The UART module consists of these key
important hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
UxRTS Pins
Prescaler
mode at 40 MIPS
mode at 40 MIPS
Buffer
(9th bit = 1)
®
Encoder and Decoder Logic
BCLK
UxRTS
UxCTS
UxRX
UxTX
®
DS70594A-page 209
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