at91sam9g15-cu ATMEL Corporation, at91sam9g15-cu Datasheet - Page 37

• Manufacturer Part Number: at91sam9g15-cu
• Description: At91sam Arm-based Embedded Mpu
• Manufacturer: ATMEL Corporation

10.11 LCD Controller (LCDC)
10.12 8-channel DMA (DMAC)
11052AS–ATARM–27-Jul-11
• Sleep Mode and conversion sequencer
• Compare level interrupt for background signal surveillance
• One Master
• Up to 266MHz input clock
• 384-byte Asynchronous Output FIFO
• One Background Layer
• One High End Overlay Layer, YUV Full planar, 4.2.0, 4.2.2 packed
• One Overlay RGB
• One Hardware cursor with user-defined size
• Up to 24 bits per Pixel in TFT Mode
• Dithering for 12bpp, 16bpp and 18bpp modes
• LUT for 1bpp, 2bpp, 4bpp and 8bpp
• Resolution Up to 2048x2048 pixels
• Supported formats:
• alpha blending, color conversion, rotation
• scaling up to 800x600 pixels
• supports RMII Mode only
• Two DMACs
• DMAC0 is full featured and optimized for memory-to-memory transfers thanks to the 64-word
• DMAC1 is optimized for peripheral-to-memory transfers, without PIP support
• Acting as Two Matrix Masters
• Embeds 8 unidirectional channels with programmable priority
• Address Generation
FIFO on channel 0
– Hardware or software trigger
– External trigger pin
– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger
– Automatic wakeup on trigger and back to sleep mode after conversions of all
– RGB: 444 (12bpp), 565 (16bpp), 666 (18bpp), 888 (24bpp and packed 24bpp)
– Transparency + RGB: 1555 (16bpp), 1666 (19bpp and packed 19bpp), 1888 (25bpp)
– Alpha + RGB or RGB + Alpha: 4444 (16bpp), 8888 (32bpp)
– Source / destination address programming
– Address increment, decrement or no change
– DMA chaining support for multiple non-contiguous data blocks through use of linked
– Scatter support for placing fields into a system memory area from a contiguous
enabled channels
lists
transfer. Writing a stream of data into non-contiguous fields in system memory
SAM9G15
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