p89lpc932ba NXP Semiconductors, p89lpc932ba Datasheet - Page 25

• Manufacturer Part Number: p89lpc932ba
• Description: P89lpc932 8-bit Microcontroller With Accelerated Two-clock 80c51 Core 8 Kb Flash With 512-byte Data Eeprom And 768-byte Ram
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12379
Product data
8.15.1 Reset vector
8.15 Reset
the RTC during Power-down, there will be high power consumption. Please use an
external low frequency clock to achieve low power with the Real-Time Clock running
during Power-down.
The P1.5/RST pin can function as either an active-LOW reset input or as a digital
input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the
external reset input function on P1.5. When cleared, P1.5 may be used as an input
pin.
Remark: During a power-up sequence, the RPE selection is overridden and this pin
will always function as a reset input. An external circuit connected to this pin
should not hold this pin LOW during a power-on sequence as this will keep the
device in reset. After power-up this input will function either as an external reset
input or as a digital input as defined by the RPE bit. Only a power-up reset will
temporarily override the selection defined by RPE bit. Other sources of reset will not
override the RPE bit.
Remark: During a power cycle, V
characteristics” on page
reset.
Reset can be triggered from the following sources:
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can
read this register to determine the most recent reset source. These flag bits can be
cleared in software by writing a ‘0’ to the corresponding bit. More than one flag bit
may be set:
Following reset, the P89LPC932 will fetch instructions from either address 0000h or
the Boot address. The Boot address is formed by using the Boot Vector as the high
byte of the address and the low byte of the address = 00h.
The Boot address will be used if a UART break reset occurs, or the non-volatile Boot
Status bit (BOOTSTAT.0) = 1, or the device is forced into ISP mode during power-on
(see P89LPC932 User’s Manual ). Otherwise, instructions will be fetched from
address 0000H.
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External reset pin (during power-up or if user configured via UCFG1);
Power-on detect;
Brownout detect;
Watchdog Timer;
Software reset;
UART break character detect reset.
During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
For any other reset, previously set flag bits that have not been cleared will remain
set.
Rev. 04 — 06 January 2004
8-bit microcontroller with accelerated two-clock 80C51 core
45) before power is reapplied, in order to ensure a power-on
DD
must fall below V
POR
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
(see
P89LPC932
Table 8 “DC electrical
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