p89lpc9402 NXP Semiconductors, p89lpc9402 Datasheet - Page 15

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p89lpc9402

Manufacturer Part Number
p89lpc9402
Description
8-bit Microcontroller With Accelerated Two-clock 80c51 Core 8 Kb 3 V Byte-erasable ?ash With 32 Segment 4 Lcd Driver
Manufacturer
NXP Semiconductors
Datasheet

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Table 4.
* indicates SFRs that are bit addressable.
[1]
[2]
[3]
[4]
[5]
[6]
Name
TAMOD
TCON*
TH0
TH1
TL0
TL1
TMOD
TRIM
WDCON
WDL
WFEED1
WFEED2
All ports are in input only (high-impedance) state after power-up.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
The RSTSRC register reflects the cause of the P89LPC9402 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on
reset value is x011 0000.
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
The only reset sources that affect these SFRs are power-on reset and watchdog reset.
Special function registers
Description
Timer 0 and 1 auxiliary
mode
Timer 0 and 1 control
Timer 0 high
Timer 1 high
Timer 0 low
Timer 1 low
Timer 0 and 1 mode
Internal oscillator trim
register
Watchdog control register
Watchdog load
Watchdog feed 1
Watchdog feed 2
Bit address
…continued
SFR
addr.
8FH
8CH
8DH
8AH
8BH
A7H
C1H
C2H
C3H
88H
89H
96H
Bit functions and addresses
T1GATE
RCCLK
PRE2
MSB
TF1
8F
-
ENCLK
T1C/T
PRE1
TR1
8E
-
TRIM.5
T1M1
PRE0
TF0
8D
-
TRIM.4
T1M2
T1M0
TR0
8C
-
T0GATE
TRIM.3
IE1
8B
-
-
WDRUN
TRIM.2
T0C/T
IT1
8A
-
WDTOF
TRIM.1
T0M1
IE0
89
-
WDCLK
TRIM.0
T0M2
T0M0
LSB
IT0
88
Reset value
Hex
00
00
00
00
00
00
00
FF
[4] [5]
[4] [6]
Binary
xxx0 xxx0
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111

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