p89lpc9402 NXP Semiconductors, p89lpc9402 Datasheet - Page 28

• Manufacturer Part Number: p89lpc9402
• Description: 8-bit Microcontroller With Accelerated Two-clock 80c51 Core 8 Kb 3 V Byte-erasable ?ash With 32 Segment 4 Lcd Driver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC9402_1
Product data sheet
7.20.2 Mode 1
7.20.3 Mode 2
7.20.4 Mode 3
7.20.5 Baud rate generator and selection
7.20.6 Framing error
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),
8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored
in RB8 in Special Function Register SCON. The baud rate is variable and is determined
by the Timer 1 overflow rate or the Baud Rate Generator (described in
“Baud rate generator and
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data
bits (LSB first), a programmable 9
transmitted, the 9
Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is
received, the 9
bit is not saved. The baud rate is programmable to either
frequency, as determined by the SMOD1 bit in PCON.
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8
data bits (LSB first), a programmable 9
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable
and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in
Section 7.20.5 “Baud rate generator and
The P89LPC9402 enhanced UART has an independent Baud Rate Generator. The baud
rate is determined by a baud rate preprogrammed into the BRGR1 and BRGR0 SFRs
which together form a 16-bit baud rate divisor value that works in a similar manner as
Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be
used for other timing functions.
The UART can use either Timer 1 or the baud rate generator output (see
that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent Baud Rate Generator uses OSCCLK.
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)
is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is
logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up
when SMOD0 is logic 0.
Fig 8.
baud rate generator
Baud rate sources for UART (Modes 1, 3)
timer 1 overflow
(CCLK-based)
(PCLK-based)
th
data bit goes into RB8 in Special Function Register SCON, while the stop
th
data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.
Rev. 01 — 22 April 2009
8-bit microcontroller with accelerated two-clock 80C51 core
selection”).
2
th
SMOD1 = 1
SMOD1 = 0
data bit, and a stop bit (logic 1). When data is
th
data bit, and a stop bit (logic 1). In fact, Mode 3 is
selection”).
SBRGS = 0
SBRGS = 1
1
16
or
P89LPC9402
baud rate modes 1 and 3
1
32
of the CPU clock
Section 7.20.5
© NXP B.V. 2009. All rights reserved.
Figure
002aaa897
8). Note
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