p89lpc9402 NXP Semiconductors, p89lpc9402 Datasheet - Page 21

• Manufacturer Part Number: p89lpc9402
• Description: 8-bit Microcontroller With Accelerated Two-clock 80c51 Core 8 Kb 3 V Byte-erasable ?ash With 32 Segment 4 Lcd Driver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC9402_1
Product data sheet
7.13.1 External interrupt inputs
7.12 Data RAM arrangement
7.13 Interrupts
The 768 bytes of on-chip RAM are organized as shown in
Table 6.
The P89LPC9402 uses a four priority level interrupt structure. This allows great flexibility
in controlling the handling of the many interrupt sources. The P89LPC9402 supports
13 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port TX, serial port
RX, combined serial port RX/TX, brownout detect, watchdog/RTC, I
comparators 1 and 2, SPI.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global
disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. If two requests of different priority
levels are pending at the start of an instruction, the request of higher priority level is
serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
The P89LPC9402 has two external interrupt inputs as well as the Keypad Interrupt
function. The two interrupt inputs are identical to those present on the standard 80C51
microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC9402 is put into Power-down or Idle
mode, the interrupt will cause the processor to wake-up and resume operation. Refer to
Section 7.16 “Power reduction modes”
Type
DATA
IDATA
•
CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC9402 has 8 kB of on-chip Code memory.
On-chip data memory usages
Data RAM
Memory that can be addressed directly and indirectly
Memory that can be addressed indirectly
Rev. 01 — 22 April 2009
8-bit microcontroller with accelerated two-clock 80C51 core
for details.
Table
P89LPC9402
6.
2
C-bus, keyboard,
© NXP B.V. 2009. All rights reserved.
Size (bytes)
128
256
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