lpc11c12 NXP Semiconductors, lpc11c12 Datasheet
lpc11c12
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lpc11c12 Summary of contents
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... The LPC11C12/C14 operate at CPU frequencies MHz. The peripheral complement of the LPC11C12/C14 includes 16/ flash memory data memory, one C_CAN controller, one Fast-mode Plus I RS-485/EIA-485 UART, two SPI interfaces with SSP features, four general purpose counter/timers, a 10-bit ADC, and 40 general purpose I/O pins ...
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... LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm LQFP48: plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 Version sot313-2 sot313-2 © NXP B.V. 2010. All rights reserved ...
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... DTR, DSR, CTS, DCD, RI, RTS CT32B0_MAT[3:0] 32-bit COUNTER/TIMER 0 CT32B0_CAP0 CT32B1_MAT[3:0] 32-bit COUNTER/TIMER 1 CT32B1_CAP0 CT16B0_MAT[2:0] 16-bit COUNTER/TIMER 0 CT16B0_CAP0 CT16B1_MAT[1:0] 16-bit COUNTER/TIMER 1 CT16B1_CAP0 CAN_TXD C_CAN CAN_RXD Fig 1. LPC11C12/C14 block diagram LPC11C12_C14_0 Preliminary data sheet 2 UART I C/ SPI RS-485 Fast SWD IRC ...
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... LPC11C12FBD48/301 LPC11C14FBD48/301 002aaf266 All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 PIO3_0/DTR R/PIO1_2/AD3/CT32B1_MAT1 R/PIO1_1/AD2/CT32B1_MAT0 R/PIO1_0/AD1/CT32B1_CAP0 R/PIO0_11/AD0/CT32B0_MAT3 PIO2_11/SCK0 PIO1_10/AD6/CT16B1_MAT1 SWCLK/PIO0_10/SCK0/CT16B0_MAT2 PIO0_9/MOSI0/CT16B0_MAT1 PIO0_8/MISO0/CT16B0_MAT0 PIO2_2/DCD/MISO1 PIO2_10 © NXP B.V. 2010. All rights reserved ...
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... PIO0_10 — General purpose digital input/output pin. SCK0 — Serial clock for SPI0. CT16B0_MAT2 — Match output 2 for 16-bit timer 0. All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 © NXP B.V. 2010. All rights reserved. ...
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... CT16B1_CAP0 — Capture input 0 for 16-bit timer 1. PIO1_9 — General purpose digital input/output pin. CT16B1_MAT0 — Match output 0 for 16-bit timer 1. All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 © NXP B.V. 2010. All rights reserved ...
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... DCD — Data Carrier Detect input for UART. PIO3_3 — General purpose digital input/output pin. RI — Ring Indicator input for UART. CAN_RXD — C_CAN receive data input. All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 © NXP B.V. 2010. All rights reserved ...
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... Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V. Output from the oscillator amplifier. Ground standard mode and I C Fast-mode Plus. All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 Figure 24). Figure 24). © NXP B.V. 2010. All rights reserved ...
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... The ARM Cortex- general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 On-chip flash program memory The LPC11C12/C14 contain 32 kB (LPC11C14 (LPC11C12) of on-chip flash memory. 7.3 On-chip SRAM The LPC11C12/C14 contain a total on-chip static RAM memory. ...
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... CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.5.1 Features • Controls system exceptions and peripheral interrupts. • In the LPC11C12/C14, the NVIC supports 32 vectored interrupts including 13 inputs to the start logic from individual GPIO pins. LPC11C12_C14_0 Preliminary data sheet 0xFFFF FFFF 3 ...
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... Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC11C12/C14 use accelerated GPIO functions: • GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing can be achieved. • ...
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... Support for modem control. 7.9 SPI serial I/O controller The LPC11C12/C14 contain two SPI controllers. Both SPI controllers support SSP features. The SPI controller is capable of operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer ...
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... C_CAN send and receive messages LPC11C12_C14_0 Preliminary data sheet 2 C-bus compliant interface with open-drain pins. The All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 multi-master bus and can be © NXP B.V. 2010. All rights reserved ...
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... CANopen SDO segmented communication primitives – CANopen SDO fall-back handler • Flash ISP programming via C_CAN supported. 7.12 10-bit ADC The LPC11C12/C14 contains one ADC single 10-bit successive approximation ADC with eight channels. 7.12.1 Features • 10-bit successive approximation ADC. • ...
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... Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Following reset, the LPC11C12/C14 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency ...
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... PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is trimmed accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC11C12/C14 use the IRC as the clock source. Software may later switch to one of the other available clock sources. ...
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... The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 μs. 7.16.3 Clock output The LPC11C12/C14 features a clock output function that routes the IRC oscillator, the system oscillator, the watchdog oscillator, or the main clock to an output pin. 7.16.4 Wake-up process The LPC11C12/C14 begin operation at power-up and when awakened from Deep power-down mode by using the 12 MHz IRC oscillator as the clock source ...
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... System control 7.17.1 Reset Reset has four sources on the LPC11C12/C14: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the IRC and initializes the flash controller ...
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... NXP Semiconductors 7.17.3 Code security (Code Read Protection - CRP) This feature of the LPC11C12/C14 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location ...
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... Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four breakpoints and two watchpoints is supported. LPC11C12_C14_0 Preliminary data sheet All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 © NXP B.V. 2010. All rights reserved ...
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... V < (1. < 125 ° based on package heat transfer, not device power consumption human body model; all pins All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 Min Max Unit 1.8 3.6 V −0.5 [2] +5.5 V [3] - 100 mA [3] - 100 ...
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... V ≤ V < 2.0 V; [14 − 2.0 V ≤ V ≤ 3.6 V; [14 1.8 V ≤ V < 2.0 V; [14 All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 [1] Typ Max Unit 3.3 3 μ 220 - ...
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... OL − 0.4 V; [14 ≥ 2 [14 0 2.0 V ≤ V ≤ 3 < 2.0 V 1.8 V ≤ V [14 All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 [1] Typ Max Unit - - − μA 50 150 −50 − ...
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... Plus pins 2.0 V ≤ V ≤ 3 1.8 V ≤ V < 2.0 V [14 [16 −0.5 −0.5 All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 [1] Typ Max Unit − μA 50 150 −50 −85 μA −50 −85 μA μ ...
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... Figure 5. Figure 5. Figure 5. = 4.5 MHz and analog input capacitance C s × All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 = 2 3 Typ Max Unit - ± LSB ± 1.5 - LSB ± 3.5 - LSB - 0.6 % ± 4 ...
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... LSB (ideal) 1018 1019 (LSB ) IA ideal 1 LSB = All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 offset gain error error 1020 1021 1022 1023 1024 − 1024 002aaf426 © ...
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... All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 Typ Max Unit ...
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... V DD − 3.3 V; active mode entered executing code DD versus temperature for different system DD All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 002aaf390 (2) 48 MHz (2) 36 MHz (2) 24 MHz (1) 12 MHz 3.0 3.6 ...
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... V; sleep mode entered from flash; all peripherals disabled in the DD versus temperature for different system DD − All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 002aaf392 (2) 48 MHz (2) 36 MHz (2) 24 MHz (1) 12 MHz temperature (° ...
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... LPC11C12_C14_0 Preliminary data sheet − °C 25 °C −40 ° 3 pin PIO0_7 All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 002aaf457 VDD = 3.6 V 3.3 V 2 temperature (°C) versus temperature for DD 002aae990 ...
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... Preliminary data sheet 0 pins PIO0_4 and PIO0_5 0.2 = 3.3 V; standard port pins and PIO0_7. DD versus LOW-level output voltage V OL All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 002aaf019 °C 25 °C −40 °C 0.4 0.6 V (V) OL versus OL 002aae991 ° ...
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... V; standard port pins. DD versus HIGH-level output source current °C 25 °C −40 ° 3.3 V; standard port pins. DD versus input voltage V pu All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 002aae992 (mA) OH 002aae988 ( © ...
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... LPC11C12_C14_0 Preliminary data sheet °C 25 °C −40 ° 3.3 V; standard port pins. DD versus input voltage V pd All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 002aae989 ( © NXP B.V. 2010. All rights reserved ...
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... C; V over specified ranges. DD Conditions t t CHCL CLCX All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 Min Typ Max [1] 10000 - - 100 105 [2] 0. ...
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... Variations between parts may cause the IRC to DD amb Conditions DIVSEL = 0x1F, FREQSEL = 0x1 in the WDTOSCCTRL register; DIVSEL = 0x00, FREQSEL = 0xF in the WDTOSCCTRL register All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 [2] Min Typ Max Unit 11.88 12 12.12 MHz ...
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... SCL clock Fast-mode Fast-mode Plus [3][4][8] data hold time Standard-mode Fast-mode Fast-mode Plus [9][10] data set-up Standard-mode time Fast-mode Fast-mode Plus All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 Min Typ Max Unit 3.0 - 5.0 ns 2.5 - 5.0 ns Min Max Unit ...
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... LOW Min 20 [1] 40 [2] 27 ≤ 3 < 2 [2] 0 [2] - [2] 0 [3][4] 0 All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 . f 2 C-bus system but the requirement t SU;DAT 2 C-bus t VD;DAT 002aaf425 Typ Max Unit - - ...
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... DATA VALID DATA VALID t DS DATA VALID t v(Q) DATA VALID DATA VALID DATA VALID DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 Typ Max Unit - - ns 3 × cy(PCLK) 2 × cy(PCLK function of the ...
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... DATA VALID DATA VALID DATA VALID t v(Q) DATA VALID DATA VALID All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 t clk( DATA VALID t CPHA = 1 h(Q) DATA VALID t CPHA = 0 h(Q) 002aae830 © NXP B.V. 2010. All rights reserved ...
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... The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in • The ADC input trace must be short and as close as possible to the LPC11C12/C14 chip. • The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines. • ...
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... Maximum crystal capacitance C series resistance R L < 180 Ω < 100 Ω < 160 Ω < 80 Ω All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 002aaf424 External load capacitors pF ...
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... C x1 output enable output pull-up enable repeater mode enable pull-down enable data input select analog input analog input All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 should be chosen smaller ESD PIN ESD weak ...
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... Reset pad configuration reset Fig 25. Reset pad configuration LPC11C12_C14_0 Preliminary data sheet GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 ESD PIN ESD V SS 002aaf274 © NXP B.V. 2010. All rights reserved. ...
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... 0.18 7.1 7.1 9.15 9.15 0.75 0.5 1 0.12 6.9 6.9 8.85 8.85 0.45 REFERENCES JEDEC JEITA MS-026 All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 SOT313 θ detail X (1) (1) θ 0.95 0.95 7 0.2 0.12 0.1 o 0.55 0.55 0 EUROPEAN ...
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... General Purpose Input/Output Phase-Locked Loop Resistor-Capacitor Service Data Object Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 © NXP B.V. 2010. All rights reserved ...
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... LPC11C12_C14_0 Preliminary data sheet Data sheet status Change notice Preliminary data sheet Table note 2 Preliminary data sheet - All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 Supersedes and Section 7.16.5.2. - © NXP B.V. 2010. All rights reserved ...
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... Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 © NXP B.V. 2010. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 00.05 — 6 May 2010 LPC11C12/C14 © NXP B.V. 2010. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: LPC11C12_C14_0 All rights reserved. Date of release: 6 May 2010 ...