lpc11c12 NXP Semiconductors, lpc11c12 Datasheet - Page 11

• Manufacturer Part Number: lpc11c12
• Description: 32-bit Cortex-m0 Microcontroller; 16/32 Flash, Sram; C_can
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC11C12_C14_0
Preliminary data sheet
7.5.2 Interrupt sources
7.7.1 Features
7.6 IOCONFIG block
7.7 Fast general purpose parallel I/O
7.8 UART
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any GPIO pin (total of 40 pins) regardless of the selected function, can be programmed to
generate an interrupt on a level, or rising edge or falling edge, or both.
The IOCONFIG block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs
can be set or cleared in one write operation.
LPC11C12/C14 use accelerated GPIO functions:
Additionally, any GPIO pin (total of 40 pins) providing a digital function can be
programmed to generate an interrupt on a level, a rising or falling edge, or both.
The LPC11C12/C14 contain one UART.
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Four programmable interrupt priority levels, with hardware priority level masking.
Relocatable vector table.
Software interrupt generation.
GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing
can be achieved.
Entire port value can be written in one instruction.
Bit level port registers allow a single instruction to set or clear any number of bits in
one write operation.
Direction control of individual bits.
All GPIO pins default to inputs with pull-ups enabled after reset except for the I
true open-drain pins PIO0_4 and PIO0_5.
Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG
block for each GPIO pin (except PIO0_4 and PIO0_5).
All information provided in this document is subject to legal disclaimers.
Rev. 00.05 — 6 May 2010
LPC11C12/C14
© NXP B.V. 2010. All rights reserved.
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C-bus
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