lpc11c12 NXP Semiconductors, lpc11c12 Datasheet - Page 20

• Manufacturer Part Number: lpc11c12
• Description: 32-bit Cortex-m0 Microcontroller; 16/32 Flash, Sram; C_can
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC11C12_C14_0
Preliminary data sheet
7.17.6 AHBLite
7.17.7 External interrupt inputs
7.17.8 Memory mapping control
7.18 Emulation and debugging
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
All GPIO pins can be level or edge sensitive interrupt inputs.
The Cortex-M0 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the NVIC.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M0 address
space. The vector table must be located on a 128 word (512 byte) boundary.
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four
breakpoints and two watchpoints is supported.
All information provided in this document is subject to legal disclaimers.
Rev. 00.05 — 6 May 2010
LPC11C12/C14
© NXP B.V. 2010. All rights reserved.
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