lpc2468fet208 NXP Semiconductors, lpc2468fet208 Datasheet - Page 29

• Manufacturer Part Number: lpc2468fet208
• Description: Lpc2468 Single-chip 16-bit/32-bit Micro; 512 Kb Flash, Ethernet, Can, Isp/iap, Usb 2.0 Device/host/otg, External Memory Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2468_2
Preliminary data sheet
7.8.1 Features
7.8 General purpose DMA controller
Note: Synchronous static memory devices (synchronous burst mode) are not supported.
The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2468
peripherals to have DMA support.
The GPDMA enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the AHB master.
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– Asynchronous page mode read
– Programmable Wait States
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait
Four chip selects for synchronous memory and four chip selects for static memory
devices
Power-saving modes dynamically control CKE and CLKOUT to SDRAMs
Dynamic memory self-refresh mode controlled by software
typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device
Separate reset domains allow the for auto-refresh through a chip reset if desired
Two DMA channels. Each channel can support a unidirectional transfer.
The GPDMA can transfer data between the 16 kB SRAM, external memory, and
peripherals such as the SD/MMC, two SSPs, and the I
Single DMA and burst DMA request signals. Each peripheral connected to the
GPDMA can assert either a burst DMA request or a single DMA request. The DMA
burst size is set by programming the GPDMA.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers.
Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
Hardware DMA channel priority. Each DMA channel has a specific hardware priority.
DMA channel 0 has the highest priority and channel 1 has the lowest priority. If
requests from two channels become active at the same time, the channel with the
highest priority is serviced first.
AHB slave DMA programming interface. The GPDMA is programmed by writing to the
DMA control registers over the AHB slave interface.
One AHB bus master for transferring data. This interface transfers data when a DMA
request goes active.
Controller supports 2 k, 4 k, and 8 k row address synchronous memory parts. That is
Rev. 02 — 16 October 2007
2
S interface.
Fast communication chip
LPC2468
© NXP B.V. 2007. All rights reserved.
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