lpc2468fet208 NXP Semiconductors, lpc2468fet208 Datasheet - Page 43

• Manufacturer Part Number: lpc2468fet208
• Description: Lpc2468 Single-chip 16-bit/32-bit Micro; 512 Kb Flash, Ethernet, Can, Isp/iap, Usb 2.0 Device/host/otg, External Memory Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2468_2
Preliminary data sheet
7.25.4.4 Power domains
7.26.1 Reset
7.26.2 Brownout detection
7.26 System control
The LPC2468 provides two independent power domains that allow the bulk of the device
to have power removed while maintaining operation of the RTC and the Battery RAM.
On the LPC2468, I/O pads are powered by the 3.3 V (V
V
the CPU and most of the peripherals.
Although both the I/O pad ring and the core require a 3.3 V supply, different powering
schemes can be used depending on the actual application requirements.
The first option assumes that power consumption is not a concern and the design ties the
V
supply for both pads, the CPU, and peripherals. While this solution is simple, it does not
support powering down the I/O pad ring “on the fly” while keeping the CPU and
peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (V
a dedicated 3.3 V supply for the CPU (V
converter powered independently from the I/O pad ring enables shutting down of the I/O
pad power supply “on the fly”, while the CPU and peripherals stay active.
The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions
require a minimum of power to operate, which can be supplied by an external battery.
When the CPU and the rest of chip functions are stopped and power removed, the RTC
can supply an alarm output that may be used by external hardware to restore chip power
and resume operation.
Reset has four sources on the LPC2468: the RESET pin, the Watchdog reset, power-on
reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input
pin. Assertion of chip Reset by any source, once the operating voltage attains a usable
level, starts the Wake-up timer (see description in
causing reset to remain asserted until the external Reset is de-asserted, the oscillator is
running, a fixed number of clocks have passed, and the flash controller has completed its
initialization.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
The LPC2468 includes 2-stage monitoring of the voltage on the V
voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt
Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the
VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a
dedicated status register.
DD(DCDC)(3V3)
DD(3V3)
and V
pins power the on-chip DC-to-DC converter which in turn provides power to
DD(DCDC)(3V3)
Rev. 02 — 16 October 2007
pins together. This approach requires only one 3.3 V power
DD(DCDC)(3V3)
Section 7.25.3 “Wake-up
). Having the on-chip DC-DC
DD(3V3)
) pins, while the
Fast communication chip
DD(3V3)
LPC2468
© NXP B.V. 2007. All rights reserved.
pins. If this
timer”),
DD(3V3)
43 of 67
) and