lpc3240 NXP Semiconductors, lpc3240 Datasheet - Page 31

• Manufacturer Part Number: lpc3240
• Description: 16/32-bit Arm Microcontrollers; Hardware ?oating-point Coprocessor, Usb On-the-go, And Emc Memory Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3220_30_40_50_1
Preliminary data sheet
7.7.2.1 Features
7.7.3.1 Features
7.7.1 Interrupt controller
7.7.2 Watchdog timer
7.7.3 Millisecond timer
7.7 System functions
To enhance the performance of the LPC3220/30/40/50 incorporates the following system
functions, an Interrupt Controller (INTC), a watchdog timer, a millisecond timer, and
several power control features. These functions are described in the following sections
The interrupt controller is comprised of three basic interrupt controller blocks, supporting a
total of 73 interrupt sources. Each interrupt source can be individually enabled/disabled
and configured for high or low level triggering, or rising or falling edge triggering. Each
interrupt may also be steered to either the FIQ or IRQ input of the ARM9. Raw interrupt
status and masked interrupt status registers allow versatile condition evaluation. In
addition to peripheral functions, each of the six general purpose input/output pins and
12 of the 22 general purpose input pins are connected directly to the interrupt controller.
The watchdog timer block is clocked by the main peripheral clock, which clocks a 32-bit
counter. A match register is compared to the Timer. When configured for watchdog
functionality, a match drives the match output low. The match output is gated with an
enable signal that gives the opportunity to generate two type of reset signal: one that only
resets chip internally, and another that goes through a programmable pulse generator
before it goes to the external pin RESOUT and to the internal chip reset.
The millisecond timer is clocked by 32 kHz RTC clock, so a prescaler is not needed to
obtain a lower count rate.
The millisecond timer includes three match registers that are compared to the
Timer/Counter value. A match can generate an interrupt and the cause the Timer/Counter
either continue to run, stop, or be reset.
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Programmable 32-bit timer.
Internally resets the device if not periodically reloaded.
Flag to indicate that a watchdog reset has occurred.
Programmable watchdog pulse output on RESOUT pin.
Can be used as a standard timer if watchdog is not used.
Pause control to stop counting when core is in debug state.
32-bit Timer/Counter, running from the 32 kHz RTC clock.
Counter or Timer operation.
Three 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Pause control to stop counting when core is in debug state.
Rev. 01 — 6 February 2009
LPC3220/30/40/50
16/32-bit ARM microcontrollers
© NXP B.V. 2009. All rights reserved.
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