lpc3240 NXP Semiconductors, lpc3240 Datasheet - Page 33

• Manufacturer Part Number: lpc3240
• Description: 16/32-bit Arm Microcontrollers; Hardware ?oating-point Coprocessor, Usb On-the-go, And Emc Memory Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3220_30_40_50_1
Preliminary data sheet
7.7.4.4 Power control modes
7.7.4.5 Reset
7.8
output to be used directly. The maximum PLL output frequency supported by the CPU is
266 MHz. The only output frequency supported by the USB PLL is 48 MHz, and the clock
has strict requirements for nominal frequency (500 ppm) and jitter (500 ps).
The LPC3220/30/40/50 supports three operational modes, two of which are specifically
designed to reduce power consumption. The modes are: Run mode, Direct Run mode,
and Stop mode.
Run mode is the normal operating mode for applications that require the CPU, AHB bus,
or any peripheral function other than the USB block to run faster than the main oscillator
frequency. In Run mode, the CPU can run at up to 266 MHz and the AHB bus can run at
up to 133 MHz.
Direct Run mode allows reducing the CPU and AHB bus rates in order to save power.
Direct Run mode can also be the normal operating mode for applications that do not
require the CPU, AHB bus, or any peripheral function other than the USB block to run
faster than the main oscillator frequency. Direct Run mode is the default mode following
chip reset.
Stop mode causes all CPU and AHB operation to cease, and stops clocks to peripherals
other than the USB block.
Reset is accomplished by an active LOW signal on the RESET input pin. A reset pulse
with a minimum width of 10 main oscillator clocks after the oscillator is stable is required to
guarantee a valid chip reset. At power-up, 10 milliseconds should be allowed for the
oscillator to start up and stabilize after V
with a minimum duration of 10 clock pulses will also be applied if the watchdog timer
generates an internal device reset.
The RESET pin is located in the RTC power domain. This means that the RTC power
must be present for an external reset to have any effect. The RTC power domain
nominally runs from 1.2 V, but the RESET pin can be driven as high as 1.95 V.
In addition to the Ethernet MAC and USB interfaces there are many more serial
communication peripheral interfaces available on the LPC3220/30/40/50. Here is a list of
the serial communication interfaces:
A short functional description of each of these peripherals is provided in the following
sections.
Communication peripheral interfaces
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Seven UARTs; four standard UARTs and three high-speed UARTs
Two SPI serial I/O controllers
Two SSP serial I/O controllers
Two I
Two I
2
2
C serial I/O controllers
S audio controllers
Rev. 01 — 6 February 2009
DD
reaches operational voltage. An internal reset
LPC3220/30/40/50
16/32-bit ARM microcontrollers
© NXP B.V. 2009. All rights reserved.
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