p89c668hbbd NXP Semiconductors, p89c668hbbd Datasheet - Page 10

• Manufacturer Part Number: p89c668hbbd
• Description: 80c51 8-bit Flash Microcontroller Family
• Manufacturer: NXP Semiconductors

*
# SFRs are modified from or added to the 80C51 SFRs.
– Reserved bits.
Philips Semiconductors
Table 1 Special Function Registers (Continued)
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an
on-chip oscillator.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. Minimum and maximum
high and low times specified in the data sheet must be observed.
This device is configured at the factory to operate using 6 clock
periods per machine cycle, referred to in this datasheet as “6 clock
mode”. (This yields performance equivalent to twice that of standard
80C51 family devices). It may be optionally configured on
commercially-available EPROM programming equipment to operate
at 12 clock periods per machine cycle, referred to in this datasheet
as “12 clock mode”. Once 12 clock mode has been configured, it
cannot be changed back to 6 clock mode.
2002 Oct 28
PSW*
RCAP2H#
RCAP2L#
SADDR#
SADEN#
S0BUF
S0CON*
SP
S1DAT#
S1ADR#
S1STA#
S1CON*#
TCON*
T2CON*
T2MOD#
TH0
TH1
TH2#
TL0
TL1
TL2#
TMOD
WDTRST
SYMBOL
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
SFRs are bit addressable.
Program Status Word
Timer 2 Capture High
Timer 2 Capture Low
Slave Address
Slave Address Mask
Serial Data Buffer
Serial Control
Stack Pointer
Serial 1 Data
Serial 1 Address
Serial 1 Status
Serial 1 Control
Timer Control
Timer 2 Control
Timer 2 Mode Control
Timer High 0
Timer High 1
Timer High 2
Timer Low 0
Timer Low 1
Timer Low 2
Timer Mode
Watchdog Timer Reset
DESCRIPTION
ADDRESS
DIRECT
CBH
CAH
DAH
DBH
CDH
CCH
D0H
A9H
B9H
D9H
D8H
C8H
C9H
8CH
8DH
8AH
8BH
A6H
99H
98H
81H
88H
89H
MSB
SM0/FE
GATE
SC4
CR2
TF1
TF2
CY
D7
DF
CF
9F
8F
–
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
ENS1
EXF2
SM1
SC3
TR1
C/T
AC
DE
CE
D6
9E
8E
–
10
RCLK
SM2
SC2
STA
TF0
DD
CD
M1
D5
9D
8D
F0
–
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (12 oscillator periods in 6 clock mode, or 24
oscillator periods in 12 clock mode), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
V
Ports 1, 2, and 3 will asynchronously be driven to their reset
condition when a voltage above V
The value on the EA pin is latched when RST is deasserted and has
no further effect.
SLAVE ADDRESS
CC
and RST must come up at the same time for a proper start-up.
TCLK
REN
RS1
SC1
STO
TR0
DC
CC
D4
9C
8C
M0
–
P89C660/P89C662/P89C664/
EXEN2
GATE
RS0
SC0
TB8
DB
IE1
CB
D3
9B
8B
SI
–
RB8
TR2
C/T
OV
IT1
D2
DA
AA
CA
9A
8A
0
–
IH1
T2OE
(min.) is applied to RST.
C/T2
CR1
IE0
D1
D9
C9
M1
F1
99
89
TI
0
CP/RL2
LSB
DCEN
CR0
GC
IT0
M0
D0
D8
C8
98
RI
88
P89C668
P
0
Product data
00000000B
00H
00H
00H
00H
xxxxxxxxB
00H
07H
00H
00H
F8H
00000000B
00H
00H
xxxxxx00B
00H
00H
00H
00H
00H
00H
00H
RESET
VALUE