p89c668hbbd NXP Semiconductors, p89c668hbbd Datasheet - Page 11

• Manufacturer Part Number: p89c668hbbd
• Description: 80c51 8-bit Flash Microcontroller Family
• Manufacturer: NXP Semiconductors

oscillator, but bringing the pin back high completes the exit. Once the
Philips Semiconductors
LOW POWER MODES
Stop Clock Mode
The static design enables the clock speed to be reduced down to
0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows
step-by-step utilization and reduces system power consumption by
lowering the clock frequency down to any value. For lowest power
consumption the Power-Down mode is suggested.
Idle Mode
In the idle mode (see Table 2), the CPU puts itself to sleep while all
of the on-chip peripherals stay active. The instruction to invoke the
idle mode is the last instruction executed in the normal operating
mode before the idle mode is activated. The CPU contents, the
on-chip RAM, and all of the special function registers remain intact
during this mode. The idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up at the
interrupt service routine and continued), or by a hardware reset
which starts the processor in the same manner as a power-on reset.
Power-Down Mode
To save even more power, a Power-Down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked Power-Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
their values down to 2.0 V and care must be taken to return V
the minimum specified operating voltages before the Power-Down
mode is terminated.
Either a hardware reset or external interrupt can be used to exit from
Power-Down. Reset redefines all the SFRs but does not change the
on-chip RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.
To properly terminate Power-Down the reset or external interrupt
should not be executed before V
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10ms).
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the
interrupt is serviced, the next instruction to be executed after RETI
will be the one following the instruction that put the device into
Power-Down.
POWER-ON FLAG
The Power-On Flag (POF) is set by on-chip circuitry when the V
level on the P89C660/662/664/668 rises from 0 to 5 V. The POF bit
can be set or cleared by software allowing a user to determine if
the reset is the result of a power-on or a warm start after
Power-Down. The V
remain unaffected by the V
Table 2. External Pin Status During Idle and Power-Down mode
2002 Oct 28
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
Idle
Idle
Power-Down
Power-Down
MODE
CC
PROGRAM MEMORY
level must remain above 3 V for the POF to
CC
External
External
Internal
Internal
level.
CC
is restored to its normal
ALE
1
1
0
0
CC
to
CC
PSEN
1
1
0
0
11
Design Consideration
When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes control.
On-chip hardware inhibits access to internal RAM in this event,
however, access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when the idle mode is terminated
by reset, the instruction following the one that invokes the idle mode
should not be one that writes to a port pin or to external memory.
ONCE
The ONCE (“On-Circuit Emulation”) mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE mode is invoked by:
1. Pulling ALE low while the device is in reset and PSEN is high;
2. Holding ALE low as RST is deactivated.
While the device is in ONCE mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the device is in this
mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
Programmable Clock-Out
A 50% duty cycle clock can be programmed to come out on P1.0.
This pin, besides being a regular I/O pin, has two alternate
functions. It can be programmed:
1. to input the external clock for Timer/Counter 2, or
2. to output a 50% duty cycle clock ranging from 122 Hz to 8 MHz
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.
The Clock-Out frequency depends on the oscillator frequency and
the reload value of Timer 2 capture registers (RCAP2H, RCAP2L)
as shown in this equation:
Where (RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L
taken as a 16-bit unsigned integer.
In the Clock-Out mode Timer 2 roll-overs will not generate an
interrupt. This is similar to when it is used as a baud-rate generator.
It is possible to use Timer 2 as a baud-rate generator and a clock
generator simultaneously. Note, however, that the baud-rate and the
Clock-Out frequency will be the same.
at a 16 MHz operating frequency (61 Hz to 4 MHz in 12 clock
mode).
n
n =
PORT 0
Data
Float
Data
Float
(65536
Mode
Oscillator Frequency
P89C660/P89C662/P89C664/
2 in 6 clock mode
4 in 12 clock mode
RCAP2H, RCAP2L)
PORT 1
Data
Data
Data
Data
PORT 2
Address
Data
Data
Data
P89C668
Product data
PORT 3
Data
Data
Data
Data