mc9s08dn60 Freescale Semiconductor, Inc, mc9s08dn60 Datasheet - Page 176

• Manufacturer Part Number: mc9s08dn60
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
176
ADLSMP
ADICLK
ADLPC
MODE
Field
ADIV
6:5
3:2
1:0
7
4
Reset:
W
R
Low Power Configuration — ADLPC controls the speed and power configuration of the successive
approximation converter. This is used to optimize power consumption when higher sample rates are not required.
0 High speed configuration
1 Low power configuration: {FC31}The power is reduced at the expense of maximum clock speed.
Clock Divide Select — ADIV select the divide ratio used by the ADC to generate the internal clock ADCK.
Table 10-6
Long Sample Time Configuration — ADLSMP selects between long and short sample time. This adjusts the
sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for
lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time
Conversion Mode Selection — MODE bits are used to select between 12-, 10- or 8-bit operation. See
Table
Input Clock Select — ADICLK bits select the input clock source to generate the internal clock ADCK. See
Table
ADLPC
10-7.
10-8.
7
0
shows the available clock configurations.
MODE
ADIV
00
01
10
11
00
01
10
11
Table 10-5. ADCCFG Register Field Descriptions
0
Figure 10-10. Configuration Register (ADCCFG)
6
ADIV
8-bit conversion (N=8)
12-bit conversion (N=12)
10-bit conversion (N=10)
Reserved
MC9S08DN60 Series Data Sheet, Rev 2
Table 10-6. Clock Divide Select
Table 10-7. Conversion Modes
0
5
Divide Ratio
1
2
4
8
ADLSMP
0
4
Mode Description
Description
0
3
MODE
Input clock ÷ 2
Input clock ÷ 4
Input clock ÷ 8
Clock Rate
Input clock
0
2
Freescale Semiconductor
0
1
ADICLK
0
0