mc9s08dn60 Freescale Semiconductor, Inc, mc9s08dn60 Datasheet - Page 81

• Manufacturer Part Number: mc9s08dn60
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this, the EMC emissions may be affected by enabling pins as high drive.
6.3
Port A, port B, and port D pins can be configured as external interrupt inputs and as an external means of
waking the MCU from stop or wait low-power modes.
The block diagram for each port interrupt logic is shown
Writing to the PTxPSn bits in the port interrupt pin select register (PTxPS) independently enables or
disables each port pin. Each port can be configured as edge sensitive or edge and level sensitive based on
the PTxMOD bit in the port interrupt status and control register (PTxSC). Edge sensitivity can be software
programmed to be either falling or rising; the level can be either low or high. The polarity of the edge or
edge and level sensitivity is selected using the PTxESn bits in the port interrupt edge select register
(PTxES).
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled port inputs must be at the
deasserted logic level. A falling edge is detected when an enabled port input signal is seen as a logic 1 (the
deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising
edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during
the next cycle.
6.3.1
A valid edge on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt request
will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in PTxSC.
6.3.2
A valid edge or level on an enabled port pin will set PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt
request will be presented to the CPU. Clearing of PTxIF is accomplished by writing a 1 to PTxACK in
PTxSC provided all enabled port inputs are at their deasserted levels. PTxIF will remain set if any enabled
port pin is asserted while attempting to clear by writing a 1 to PTxACK.
Freescale Semiconductor
PTxn
PTxn
PTxES0
PTxESn
Pin Interrupts
1
0
1
0
S
S
Edge Only Sensitivity
Edge and Level Sensitivity
PTxPS0
PTxPSn
Figure 6-2. Port Interrupt Block Diagram
MC9S08DN60 Series Data Sheet, Rev 2
PTxMOD
V
DD
D
CK
CLR
Q
Figure
INTERRUPT FF
PORT
6-2.
RESET
PTxACK
STOP
Chapter 6 Parallel Input/Output Control
SYNCHRONIZER
STOP BYPASS
BUSCLK
PTxIE
PTxIF
PTx
INTERRUPT
REQUEST
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