mc9s08qd4 Freescale Semiconductor, Inc, mc9s08qd4 Datasheet - Page 151
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mc9s08qd4
Manufacturer Part Number
mc9s08qd4
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S08QD4.pdf
(202 pages)
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11.3.2
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The
coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPMxCNTH or
TPMxCNTL, or any write to the timer status/control register (TPMxSC).
Reset clears the TPM counter registers.
Freescale Semiconductor
Reset
W
R
Bit 15
Timer Counter Registers (TPMxCNTH:TPMxCNTL)
1
2
0
7
The maximum frequency that is allowed as an external clock is one-fourth of the bus
frequency.
If the external clock input is shared with channel n and is selected as the TPM clock source,
the corresponding ELSnB:ELSnA control bits must be set to 0:0 so channel n does not try to
use the same pin for a conflicting function.
CLKSB:CLKSA
PS2:PS1:PS0
0:0
0:1
1:0
1:1
14
Figure 11-4. Timer Counter Register High (TPMxCNTH)
0
6
0:0:0
0:0:1
0:1:0
0:1:1
1:0:0
1:0:1
1:1:0
1:1:1
Table 11-2. TPM Clock Source Selection
MC9S08QD4 Series MCU Data Sheet, Rev. 3
Table 11-3. Prescale Divisor Selection
Any write to TPMxCNTH clears the 16-bit counter.
13
0
5
TPM Clock Source to Prescaler Input
No clock selected (TPMx disabled)
12
0
4
External source (TPMxCLK)
Fixed system clock (XCLK)
Bus rate clock (BUSCLK)
TPM Clock Source Divided-By
11
3
0
128
16
32
64
1
2
4
8
Timer/Pulse-Width Modulator (S08TPMV2)
10
0
1,2
2
9
0
1
Bit 8
0
0
151