mc9s08qd4 Freescale Semiconductor, Inc, mc9s08qd4 Datasheet - Page 56
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mc9s08qd4
Manufacturer Part Number
mc9s08qd4
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S08QD4.pdf
(202 pages)
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Chapter 5 Resets, Interrupts, and General System Control
5.5.1
Figure 5-1
(SP) points at the next available byte location on the stack. The current values of CPU registers are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack which is the address that is one less than
the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part
of the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR.
Typically, the flag is cleared at the beginning of the ISR so that if another interrupt is generated by this
same source, it will be registered so it can be serviced after completion of the current ISR.
5.5.2
External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)
can wake the MCU.
5.5.2.1
The IRQ pin enable (IRQPE) control bit in IRQSC must be 1 in order for the IRQ pin to act as the interrupt
request (IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels detected
(IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an event
causes an interrupt or only sets the IRQF flag which can be polled by software.
56
shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
Interrupt Stack Frame
External Interrupt Request (IRQ) Pin
Pin Configuration Options
STACKING
ORDER
UNSTACKING
5
4
3
2
1
ORDER
MC9S08QD4 Series MCU Data Sheet, Rev. 3
1
2
3
4
5
Figure 5-1. Interrupt Stack Frame
* High byte (H) of index register is not automatically stacked.
7
INDEX REGISTER (LOW BYTE X)
CONDITION CODE REGISTER
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
ACCUMULATOR
TOWARD HIGHER ADDRESSES
TOWARD LOWER ADDRESSES
*
0
SP AFTER
INTERRUPT STACKING
SP BEFORE
THE INTERRUPT
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