mc9s08ac32 Freescale Semiconductor, Inc, mc9s08ac32 Datasheet - Page 251

• Manufacturer Part Number: mc9s08ac32
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 15
Timer/PWM (S08TPMV3)
15.1
The MC9S08AC60 Series includes three independent timer/PWM (TPM) modules which support
traditional input capture, output compare, or buffered edge-aligned pulse-width modulation (PWM) on
each channel. The timer system in the MC9S08AC60 Series includes a 6-channel TPM1, a separate
2-channel TPM2 and a separate 2-channel TPM3.
A control bit in each TPM configures all channels in that timer to operate as center-aligned PWM
functions. In each TPM, timing functions are based on a separate 16-bit counter with prescaler and modulo
features to control frequency and range (period between overflows) of the time reference.
The use of the fixed system clock, XCLK, as the clock source for any of the TPM modules allows the TPM
prescaler to run using the oscillator rate divided by two (ICGERCLK/2). This option is only available if
the ICG is configured in FEE mode and the proper conditions are met (see
Generator
as BUSCLK.
An external clock source can be connected to the TPMxCLK pin. The maximum frequency for TPMxCLK
is the bus clock frequency divided by 4. For the MC9S08AC60 Series, TPMCLK, TPM1CLK, and
TPM2CLK options are configured via software using the TPMCCFG bit in the SOPT2 register; out of
reset, TPM1CLK, and TPM2CLK, and TPMCLK is connected to TPM1, TPM2, and TPM3 respectively.
(TPMCCFG = 1).
15.2
Timer system features include:
Freescale Semiconductor
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Clock source to prescaler for each TPM is independently selectable as bus clock, fixed system
clock, or an external pin.
16-bit free-running or up/down (CPWM) count operation
16-bit modulus register to control counter range
Timer system enable
One interrupt per channel plus a terminal count interrupt for each TPM module
Each channel may be input capture, output compare, or buffered edge-aligned PWM
Rising-edge, falling-edge, or any-edge input capture trigger
Set, clear, or toggle output compare action
Selectable polarity on PWM outputs
Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all
channels
Introduction
Features
(S08ICGV4)”). In all other ICG modes this selection is redundant because XCLK is the same
MC9S08AC60 Series Data Sheet, Rev. 2
Chapter 10, “Internal Clock
251