mc9s08jm60 Freescale Semiconductor, Inc, mc9s08jm60 Datasheet - Page 35

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mc9s08jm60

Manufacturer Part Number
mc9s08jm60
Description
Hcs08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Chapter 3
Modes of Operation
3.1
The operating modes of the MC9S08JM60 series are described in this chapter. Entry into each mode, exit
from each mode, and functionality while in each mode are described.
3.2
3.3
Run is the normal operating mode for the MC9S08JM60 series. This mode is selected upon the MCU
exiting reset if the BKGD/MS pin is high. In this mode, the CPU executes code from internal memory with
execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset.
3.4
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC, together with the on-chip in-circuit emulator (ICE) debug module (DBG),
provides the means for analyzing MCU operation during software development.
Active background mode is entered in any of five ways:
Freescale Semiconductor
Active background mode for code development
Wait mode:
— CPU halts operation to conserve power
— System clocks running
— Full voltage regulation is maintained
Stop modes: CPU and bus clocks stopped
— Stop2: Partial power down of internal circuits; RAM and USB RAM contents retained
— Stop3: All internal circuits powered for fast recovery; RAM, USB RAM, and register contents
When the BKGD/MS pin is low at the rising edge of reset
When a BACKGROUND command is received through the BKGD pin
When a BGND instruction is executed
When encountering a BDC breakpoint
When encountering a DBG breakpoint
Introduction
Features
Run Mode
Active Background Mode
are retained
MC9S08JM60 Series Data Sheet, Rev. 2
35

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