mc9s08jm60 Freescale Semiconductor, Inc, mc9s08jm60 Datasheet - Page 72

• Manufacturer Part Number: mc9s08jm60
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 5 Resets, Interrupts, and System Configuration
5.7
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to the direct-page register summary in
address assignments for all registers. This section refers to registers and control bits only by their names.
A Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of
5.7.1
This direct page register includes status and control bits, which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
72
IRQEDG
IRQPDD
Reset
IRQPE
Field
IRQF
6
5
4
3
W
R
Reset, Interrupt, and System Control Registers and Control Bits
Interrupt Pin Request Status and Control Register (IRQSC)
Interrupt Request (IRQ) Pull Device Disable — This read/write control bit is used to disable the internal pullup
device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device enabled if IRQPE = 1.
1 IRQ pull device disabled if IRQPE = 1.
Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or
levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is
sensitive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is configured
to detect rising edges, the optional pullup resistor is re-configured as an optional pulldown resistor.
0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.
IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can
be used as an interrupt request.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
0
0
7
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
= Unimplemented or Reserved
Operation.”
IRQPDD
0
6
Table 5-2. IRQSC Register Field Descriptions
IRQEDG
MC9S08JM60 Series Data Sheet, Rev. 2
0
5
Chapter 4,
IRQPE
0
4
Description
“Memory,” of this data sheet for the absolute
IRQF
3
0
IRQACK
0
0
2
Freescale Semiconductor
IRQIE
0
1
IRQMOD
0
0