mc9s08jm60 Freescale Semiconductor, Inc, mc9s08jm60 Datasheet - Page 78

• Manufacturer Part Number: mc9s08jm60
• Description: Hcs08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 5 Resets, Interrupts, and System Configuration
5.7.8
This register is used to report the status of the low voltage warning function, and to configure the stop
mode behavior of the MCU.
78
Any other Reset:
1
Power-on Reset:
LVWACK
LVDRE
LVDSE
This bit can be written only one time after reset. Additional writes are ignored.
LVWIE
BGBE
LVWF
LVDE
Field
7
6
5
4
3
2
0
LVD Reset:
System Power Management Status and Control 2 Register
(SPMSC2)
Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2)
Low-Voltage Warning Flag — The LVWF bit indicates the low-voltage warning status.
0 low-voltage warning is not present.
1 low-voltage warning is present or was present.
Low-Voltage Warning Acknowledge — If LVWF = 1, a low-voltage condition has occurred. To acknowledge this
low-voltage warning, write 1 to LVWACK, which will automatically clear LVWF to 0 if the low-voltage warning is
no longer present.
Low-Voltage Warning Interrupt Enable — This bit enables hardware interrupt requests for LVWF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVWF = 1.
Low-Voltage Detect Reset Enable — This write-once bit enables LVD events to generate a hardware reset
(provided LVDE = 1).
0 LVD events do not generate hardware resets.
1 Force an MCU reset when an enabled low-voltage detect event occurs.
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by
ACMP or ADC module on one of its internal channels.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.
W
R
0
0
0
0
7
= Unimplemented or Reserved
Table 5-10. SPMSC1 Register Field Descriptions
0
0
0
0
6
MC9S08JM60 Series Data Sheet, Rev. 2
LVDV
0
u
u
5
LVWV
4
0
u
u
Description
u = Unaffected by reset
PPDF
0
0
0
3
PPDACK
0
0
0
0
2
Freescale Semiconductor
0
0
0
0
1
PPDC
0
0
0
0
1