mc56f8006 Freescale Semiconductor, Inc, mc56f8006 Datasheet
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... This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: MC56F8006 MC56F8006/MC56F8002 48-pin LQFP Case: 932- ...
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... MC56F8006/MC56F8002 Family Configuration . . . . . . . . . . . .3 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 Overview 3.1 56F8006/56F8002 Features . . . . . . . . . . . . . . . . . . . . . .4 3.2 Award-Winning Development Environment 3.3 Architecture Block Diagram 3.4 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . .11 4 Signal/Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . .11 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3 56F8006/56F8002 Signal Pins . . . . . . . . . . . . . . . . . . .16 5 Memory Maps .28 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 5.2 Program Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 5.3 Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.4 Interrupt Vector Table and Reset Vector . . . . . . . . . . . .30 5 ...
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... Power management controller (PMC) IEEE 1149.1 Joint Test Action Group (JTAG) interface Enhanced on-chip emulator (EOnCE) IEEE 1149.1 Joint Test Action Group (JTAG) interface 1 Some ADC inputs share the same pin. See MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor MC56F8006/MC56F8002 Family Configuration Table 1. 28-pin ...
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... Block Diagram 2 Block Diagram Figure 1shows a top-level block diagram of the MC56F8006/MC56F8002 digital signal controller. Package options for this family are described later in this document. Italics indicate a 56F8002 device parameter. PWM 6 PWM Outputs 3 Fault Inputs programmable delay block ADCA 24 Total PGA/ADC ADCB ...
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... One multi-function, six-output pulse width modulator (PWM) module — MHz PWM operating clock — 15 bits of resolution — Center-aligned and edge-aligned PWM signal mode — Phase shifting PWM pulse generation — Four programmable fault inputs with programmable digital filter MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Overview 5 ...
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... One serial communication interface (SCI) with LIN slave functionality — MHz operating clock — Full-duplex or single-wire operation — Programmable bit data format — Two receiver wakeup methods: – Idle line – Address mark — 1/16 bit-time noise detection MC56F8006/MC56F8002 Digital Signal Controller, Rev Freescale Semiconductor ...
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... Phase lock loop (PLL) provides a high-speed clock to the core and peripherals — Provides 3x system clock to PWM and dual timer and SCI — Loss of lock interrupt — Loss of reference clock interrupt • Clock sources MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor 2 C) port Overview 7 ...
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... A full set of programmable peripherals — PWM, PGAs, ADCs, SCI, SPI, I various applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals can also be used as general-purpose input/outputs (GPIOs). MC56F8006/MC56F8002 Digital Signal Controller, Rev PIT, timers, and analog comparators — supports ...
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... IPBus interface and the internal connections among each unit of the 56800E core. Figure 3 shows the peripherals and control blocks connected to the IPBus bridge. Please see the system integration module (SIM) section in the MC56F8006 Reference Manual for information about which signals are multiplexed with those of other peripherals. Program Control Unit ...
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... Overview IPBus Bridge System Clock Trigger A MC56F8006/MC56F8002 Digital Signal Controller, Rev RTC COP Second Clcok source COSC OCCS ROSC SIM PMC 1KHz INTC SPI SCI I2C Dual Timer (TMR) PWM PWM Synch PWM Input Mux CMP0 CMP1 CMP2 PDB ADCA ...
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... Programmable Delay Block (PDB) Clock JTAG/Enhanced On-Chip Emulation (EOnCE 1 Pins may be shared with other peripherals. See MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Description 4, each table row describes the signal or signals present on a pin, sorted by pin number. Table 3. Functional Group Pin Allocations ...
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... RESET/GPIOA7 GPIOB3/MOSI/TIN3/ANA3 and ANB3/PWM5/CMP1_OUT 17 25 GPIOB2/MISO/TIN2/ANA2 and ANB2/CMP0_OUT GPIOA6/FAULT0/ANA1 and ANB1/SCL/TXD/CLKO_1 GPIOB4/T0/CLKO_0/MISO/ SDA/RXD/ANA0 and ANB0 MC56F8006/MC56F8002 Digital Signal Controller, Rev Table 4. 56F8006/56F8002 Pins 2 GPIO I C SCI SPI ADC PGA 1 B6 SDA RXD ANA13 1 B1 SDA SS ANA12 ...
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... TMS/GPIOD3/ANB11/T1/ CMP1_OUT TDO/GPIOD1/ANB10/T0/ CMP2_OUT 1 Shielded ADC input. 4.2 Pin Assignment MC56F8006 and MC56F8002 28-pin small outline IC (28SOIC) assignment is shown in low-profile quad flat pack (32LQFP) is shown in in Figure 6. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Table 4. 56F8006/56F8002 Pins (continued) 2 GPIO I C SCI ...
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... ANA9 & PGA0– & CMP2_P4/GPIOC2 ANA7 & PGA0+ & CMP2_M2/GPIOC1 ANA5 and CMP1_M1/GPIOC0/FAULT0 TCK/GPIOD2/ANA4 & CMP1_P2/CMP2_OUT RESET/GPIOA7 GPIOB3/MOSI/TIN3/ANA3 & ANB3/PWM5/CMP1_OUT GPIOA6/FAULT0/ANA1 & ANB1/SCL/TXD/CLKO_1 GPIOB4/T0/CLKO_0/MISO/SDA/RXD/ANA0 & ANB0 GPIOA5/PWM5/FAULT2 or EXT_SYNC/TIN3 Figure 4. Top View, MC56F8006/MC56F8002 28-Pin SOIC Package MC56F8006/MC56F8002 Digital Signal Controller, Rev ...
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... GPIOB1/SS/SDA/ANA12 & CMP2_P3 GPIOB7/TXD/SCL/ANA11 & CMP2_M3 GPIOB5/T1/FAULT3/SCLK ANB8 and PGA1+ & CMP0_M2/GPIOC4 ANB6 and PGA1– & CMP0_P4/GPIOC5 ANB4 & CMP1_P1/GPIOC6/PWM2 V DDA Figure 5. Top View, MC56F8006 32-Pin LQFP Package MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor ORIENTATION ...
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... GPIOC7/ANB5 & CMP1_M2 ANB4 & CMP1_P1/GPIOC6/PWM2 V DDA Figure 6. Top View, MC56F8006 48-Pin LQFP Package 4.3 56F8006/56F8002 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed via the GPIO module’s peripheral enable registers (GPIO_x_PER) and SIM module’s (GPS_xn) GPIO peripheral select registers. If CLKIN or XTAL is selected as device external clock input, the CLK_MOD bit in the OCCS oscillator control register (OSCTL) needs to be set too ...
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... GPIOA1 (PWM1) GPIOA2 23 35 (PWM2) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor State Type During Reset Supply Supply I/O Power — This pin supplies 3.3 V power to the chip I/O interface. Supply Supply I/O Ground — These pins provide ground for chip I/O interface. ...
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... Input/Open (FAULT1) (TIN2) GPIOA5 (PWM5) (FAULT2/ EXT_SYNC) (TIN3) MC56F8006/MC56F8002 Digital Signal Controller, Rev State Type During Reset Input/ Input, Port A GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup enabled Output PWM3 — ...
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... Input/Open (TXD) (CLKO_1) GPIOB0 (SCLK) (SCL) Input/Open (ANB13) (PWM3) (T1) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor State Type During Reset Input/ Input, Port A GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Input enabled FAULT0 — ...
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... Input/Open (ANA12 and CMP2_P3) GPIOB2 17 25 (MISO) (TIN2) (ANA2 and ANB2) (CMP0_ OUT) MC56F8006/MC56F8002 Digital Signal Controller, Rev State Type During Reset Input/ Input, Port B GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup ...
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... OUT GPIOB4 (T0) (CLKO_0) (MISO) (SDA) Input/Open (RXD) (ANA0 and ANB0) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor State Type During Reset Input/ Input, Port B GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Input/ enabled MOSI — ...
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... Input/Open (ANA13 and CMP0_P2) (CLKIN) GPIOB7 3 3 (TXD) (SCL) Input/Open (ANA11 and CMP2_M3) MC56F8006/MC56F8002 Digital Signal Controller, Rev State Type During Reset Input/ Input, Port B GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup ...
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... ANA9 and PGA0– and CMP2_P4 (GPIOC2) GPIOC3 46 (EXT_ TRIGGER) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor State Type During Reset Analog Analog ANA5 and CMP1_M1— Analog input to channel 5 of ADCA and Input Input negative input 1 of analog comparator 1. ...
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... ANB4 and CMP1_P1 (GPIOC6) (PWM2) GPIOC7 10 (ANB5 and CMP1_M2) MC56F8006/MC56F8002 Digital Signal Controller, Rev State Type During Reset Analog Analog ANB8 and PGA1+ and CMP0_M2 — Analog input to channel 8 of Input Input ADCB and PGA1 positive input and negative input 2 of analog comparator 0 ...
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... OUT) TCK (GPIOD2) (ANA4 and CMP1_P2) (CMP2_ OUT) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor State Type During Reset Input Input, Test Data Input — This input pin provides a serial input data stream internal to the JTAG/EOnCE port sampled on the rising edge of TCK pullup and has an on-chip pullup resistor ...
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... CMP0_M1) GPIOE3 14 (ANA10 and CMP2_M1) GPIOE4 18 (ANA6 and CMP2_P2) MC56F8006/MC56F8002 Digital Signal Controller, Rev State Type During Reset Input Input, Test Mode Select Input — This input pin is used to sequence the internal JTAG TAP controller’s state machine sampled on the rising pullup edge of TCK and has an on-chip pullup resistor ...
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... GPIOF0 (XTAL) GPIOF1 40 (CMP1_P3) GPIOF2 41 (CMP0_M3) GPIOF3 42 (CMP0_P3) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor State Type During Reset Input/ Input, Port E GPIO — This GPIO pin can be individually programmed as Output internal an input or output pin. pullup Analog enabled ANA8 and CMP2_P1— Analog input to channel 8 of ADCA and Input positive input 1 of analog comparator 2 ...
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... P: 0x00 1FFF P: 0x00 0000 1 All addresses are 16-bit word addresses. 2 This RAM is shared with data space starting at address X: 0x00 0000; see MC56F8006/MC56F8002 Digital Signal Controller, Rev Table 6. Flash memories’ restrictions are identified in the “Use Table 6. Chip Memory Configurations 56F8002 ...
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... X:0x00 0400 X:0x00 03FF X:0x00 0000 1 All addresses are 16-bit word addresses. 2 This RAM is shared with Program space starting at P: 0x00 8000. See Figure 8. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor 1 for 56F8002 at Reset (continued) Memory Allocation RESERVED 2 On-Chip RAM : 2 KB RESERVED • ...
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... VAB[20:0]. The lower seven bits are determined based on the highest priority interrupt and are then appended onto VBA before presenting the full VAB to the core. Please see the MC56F8006 Peripheral Reference Manual for detail. The reset startup addresses of 56F8002 and 56F8006 are different. ...
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... GPIO Port F System Integration Module Power Management Controller Analog Comparator 0 Analog Comparator 1 Analog Comparator 2 Programmable Interval Timer Programmable Delay Block Real Timer Clock Flash Memory Interface MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Prefix TMR PWM INTC ADCA ADCB PGA0 PGA1 ...
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... X:0xFF FF90 X:0xFF FF8F X:0xFF FF8E X:0xFF FF8D X:0xFF FF8C X:0xFF FF8B X:0xFF FF8A X:0xFF FF89 – X:0xFF FF00 MC56F8006/MC56F8002 Digital Signal Controller, Rev Table 11. EOnCE Memory Map OTX1/ORX1 OTX/ORX (32 bits) OTXRXSR Transmit and Receive Status and Control Register OCLSR ...
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... Ability to power down the internal relaxation oscillator or crystal oscillator • Ability to put the internal relaxation oscillator into standby mode • Ability to power down the PLL MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor and V are also the voltage reference high and voltage reference low inputs, SSA ...
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... The center frequency of the internal oscillator is calibrated at the factory to 8 MHz and the TRIM value is stored in the flash information block and loaded to the FMOPT1 register at reset. When using the relaxation oscillator, the boot code should read the FMOPT1 register and set this value as OSCTL TRIM. For further information, see the MC56F8006 Peripheral Reference Manual. ...
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... XTAL and the EXTAL pin is grounded or configured as GPIO while CLK_MOD bit in OSCTL register is set. The external clock input must be generated using a relatively low impedance driver with maximum frequency less than 8 MHz. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor General System Control Information ...
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... The SIM is responsible for the following functions: • Chip reset sequencing • Core and peripheral clock control and distribution • Stop/wait mode control • System status control MC56F8006/MC56F8002 Digital Signal Controller, Rev 56F8006/56F8002 XTAL EXTAL External Clock GND or GPIO (<50 MHz) Figure 13 ...
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... The PDB pre-trigger A and trigger A outputs are connected to the ADCA and PGA0 hardware trigger inputs. The PDB pre-trigger B and trigger B outputs are connected to the ADCB and PGA1 hardware trigger inputs. When the input trigger of PDB is asserted, PDB trigger and pre-trigger outputs are asserted after a delay of a pre-programmed period. See the MC56F8006 Peripheral Reference Manual for additional information. ...
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... The inclusion of such a back door technique is at the discretion of the system designer. MC56F8006/MC56F8002 Digital Signal Controller, Rev NOTE ...
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... After the data register has been updated, you must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence is complete. Refer to the MC56F8006 Peripheral Reference Manual for detail, or contact Freescale. ...
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... JTAG/EOnCE port. Refer to the MC56F8006 Peripheral Reference Manual for detail. The key must be entered in four consecutive accesses to the flash, so this routine should be designed to run in RAM ...
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... Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, use normal handling precautions to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Table 12. Absolute Maximum Ratings ...
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... I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take P the difference between actual pin voltage and V unusually high pin current (heavy loads), the difference between pin voltage and V MC56F8006/MC56F8002 Digital Signal Controller, Rev Description Symbol ...
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... Junction to board Junction to case Junction to package top Table 17. 48LQFP Package Thermal Characteristics Characteristic Junction to ambient Natural convection Junction to ambient Natural convection Junction to ambient (@200 ft/min) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Comments Symbol Single layer board R θJA (1s) Four layer board R θJMA ...
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... Using relaxation oscillator Using external clock source Input Voltage High (digital inputs) Input Voltage Low (digital inputs) Oscillator Input Voltage High XTAL driven by an external clock source Oscillator Input Voltage Low MC56F8006/MC56F8002 Digital Signal Controller, Rev Comments Symbol Four layer board R θJMA ...
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... This section includes information about power supply requirements and I/O pin characteristics. Characteristic Operating Voltage Output high All I/O pins, voltage low-drive strength All I/O pins, high-drive strength Output high Max total I current MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor ( REFL x SSA SS Symbol Notes 1 min.) ...
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... All functional non-supply pins are internally clamped Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. MC56F8006/MC56F8002 Digital Signal Controller, Rev Table 20. DC Characteristics Symbol ...
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... I (mA) OL Figure 16. Typical Low-Side Driver (Sink) Characteristics — Low Drive (GPIO_x_DRIVEn = 0) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor range during instantaneous and operating maximum DD > greater than 85°C 40 25°C –40° ...
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... Figure 18. Typical High-Side (Source) Characteristics — Low Drive (GPIO_x_DRIVEn = 0) TYPICAL V – 0.8 85°C 25°C 0.6 –40°C 0.4 0 –5 –10 – Figure 19. Typical High-Side (Source) Characteristics — High Drive (GPIO_x_DRIVEn = 1) MC56F8006/MC56F8002 Digital Signal Controller, Rev 3 0.4 0.3 0 ...
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... MHz device clock relaxation oscillator (ROSC) in high speed mode; PLL engaged; all peripheral module and core clocks are off; ADC/DAC/comparator powered off; processor core in stop state MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Table 21. Supply Current Consumption Typical @ 3.3 V, 25°C Conditions I 45.6 mA 573.06 μ ...
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... Program time 2 Erase time Mass erase time 1 There is additional overhead that is part of the programming sequence. See the MC56F8006 Peripheral Reference Manual for detail. 2 Specifies page erase time. There are 512 bytes per page in the program flash memory. MC56F8006/MC56F8002 Digital Signal Controller, Rev Table 21 ...
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... From powerdown to powerup state at 32 MHz system clock state. 5 This is measured on the CLKO signal (programmed as system clock) over 264 system clocks at 32 MHz system clock frequency and using an 8 MHz oscillator frequency. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Symbol Min ...
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... This is the time required from standby to normal mode transition required to meet QSCI requirements See Figure 21. 8.16 8.08 8 7.92 7.84 -50 -25 Figure 21. Relaxation Oscillator Temperature Variation (Typical) After Trim MC56F8006/MC56F8002 Digital Signal Controller, Rev Table 25. Relaxation Oscillator Timing Symbol Minimum 1 f — — roscs t — jitterrosc 3 4 — ...
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... At 4 MHz (used coming out of reset and stop modes 250 ns. 2 Parameters listed are guaranteed by design. GPIO pin (Input) Figure 22. GPIO Interrupt Timing (Negative Edge-Sensitive) 8.12 External Oscillator (XOSC) Characteristics Reference Figure 9, and Figure 10, and MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor NOTE Symbol Typical Min 96T ...
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... Fall Time Figure 23. Input Signal Measurement References Figure 24 shows the definitions of the following signal states: • Active state, when a bus or signal is driven, and enters a low impedance state MC56F8006/MC56F8002 Digital Signal Controller, Rev Table 27. Crystal Oscillator Characteristics and series resistor (R ...
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... Master Slave Data hold time required for inputs Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) Slave MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor and Data2 Valid Data2 Data Three-stated Figure 24 ...
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... Slave Fall time Master Slave 1 Parameters listed are guaranteed by design. SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output MISO (Input) MOSI (Output) MC56F8006/MC56F8002 Digital Signal Controller, Rev Table 28. SPI Timing Symbol Min t DV — — — — ...
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... MISO (Input) t (ref) DV MOSI (Output) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor SS is held High on master MSB in Bits 14– Master MSB out Bits 14– ...
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... Minimum break character length 1 Parameters listed are guaranteed by design the frequency of operation of the SCI in MHz, which can be selected system clock (max. 32 MHz system clock MAX (max. 96 MHz) for the 56F8006/56F8002 device. MC56F8006/MC56F8002 Digital Signal Controller, Rev ...
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... Set-up time for STOP t SU; STO condition Bus free time between STOP and START condition Pulse width of spikes that must be suppressed by the input filter MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor RXD PW Figure 29. RXD Pulse Width TXD PW Figure 30. TXD Pulse Width 2 C) Timing 2 Table 30 ...
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... TCK low to TDO tri-state 1 TCK frequency of operation must be less than 1/8 the processor rate. TCK (Input – MC56F8006/MC56F8002 Digital Signal Controller, Rev bus system, but the requirement SU; DAT f t SU; STA SR t HIGH Table 31. JTAG Timing ...
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... Timer input high/low period Timer output period Timer output high/low period 1 In the formulas listed the clock cycle. For 32 MHz operation 31.25ns. 2. Parameters listed are guaranteed by design. Timer Inputs Timer Outputs MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor t DS Input Data Valid ...
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... Sampling frequency (pga_clk_2p5) normal mode (pga_lp_2p5 asserted) low power mode (pga_lp_2p5 negated) Input signal bandwidth General Purpose mode (BP=1) Internal voltage doubler clock frequency(pga_clk_doubler_2p5) Operating temperature MC56F8006/MC56F8002 Digital Signal Controller, Rev Table 33. COP Specifications Symbol LPFosc IDD Table 34. PGA Specifications Symbol ...
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... REFL SSA REFH DDA – Figure 35. ADC Input Impedance Equivalency Diagram MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Table 35. ADC Operating Conditions Symb Min ADIN REFL C — ADIN R — ADIN R AS — — — ...
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... Input leakage 12-bit mode error 10-bit mode 8-bit mode Temp sensor –40°C–25°C slope 25°C–125°C Temp sensor 25°C voltage MC56F8006/MC56F8002 Digital Signal Controller, Rev REFH DDA Symb Min Typ I — 120 DDAD I — ...
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... Optimize Power Consumption See Section 8.6, “Supply Current Characteristics,” for a list of I provides additional detail that can be used to optimize power consumption for a given application. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor =1.0 MHz unless otherwise stated. Typical values are for ADCK Table 37. HSCMP Specifications ...
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... IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs driving 10 mA into LEDs, then P = 8*0.5*0. mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored assumed to be negligible. MC56F8006/MC56F8002 Digital Signal Controller, Rev internal [static component] ...
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... The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about wire extending from the MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor , can be obtained from the equation: ...
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... These internal pullups can be disabled by software. To eliminate PCB trace impedance effect, each ADC input should have a no less than Ω RC filter. • • External clamp diodes on analog input pins are recommended. MC56F8006/MC56F8002 Digital Signal Controller, Rev CAUTION , V , and V ...
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... Small Outline IC (SOIC) MC56F8006 1.8–3.6 V Small Outline IC (SOIC) MC56F8006 1.8–3.6 V Low-Profile Quad Flat Pack MC56F8006 1.8–3.6 V Low-Profile Quad Flat Pack 1 This package is RoHS compliant. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Pin Frequency Package Type Count (LQFP) 48 (LQFP) Design Considerations ...
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... Package Mechanical Outline Drawings 10 Package Mechanical Outline Drawings 10.1 28-pin SOIC Package MC56F8006/MC56F8002 Digital Signal Controller, Rev Freescale Semiconductor ...
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... MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Package Mechanical Outline Drawings 71 ...
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... Package Mechanical Outline Drawings Figure 36. 56F8006/56F8002 28-Pin SOIC Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev Freescale Semiconductor ...
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... LQFP MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Package Mechanical Outline Drawings 73 ...
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... Package Mechanical Outline Drawings MC56F8006/MC56F8002 Digital Signal Controller, Rev Freescale Semiconductor ...
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... Figure 37. 56F8006/56F8002 32-Pin LQFP Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Package Mechanical Outline Drawings 75 ...
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... Package Mechanical Outline Drawings 10.3 48-pin LQFP MC56F8006/MC56F8002 Digital Signal Controller, Rev Freescale Semiconductor ...
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... Figure 38. 56F8006/56F8002 48-Pin LQFP Mechanical Information MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Package Mechanical Outline Drawings 77 ...
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... All level 3 interrupts are serviced before level 2 and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the vector base address (VBA). Please see the MC56F8006 Peripheral Reference Manual for detail. ...
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... USER6 vector can be defined as a fast interrupt if the instruction located in this vector location is not a JSR or BSR instruction. Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference Manual for detail. MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2 Freescale Semiconductor Table 40. Interrupt Vector Table Contents Priority ...
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Appendix B Peripheral Register Memory Map and Reset Value Offset Reset Bit Addr. Value Periph. Register 15 (Hex) (Hex) TMR0_ 00 0000 TMR0 COMP1 TMR0_ 01 0000 TMR0 COMP2 TMR0_ 02 0000 TMR0 CAPT TMR0_ 03 0000 TMR0 LOAD TMR0_ ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) 0C–0E — TMR0 Reserved TMR_ 0F 000F TMR0 0 ENBL TMR1_ 10 0000 TMR1 COMP1 TMR1_ 11 0000 TMR1 COMP2 TMR1_ 12 ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) 1C–1F — TMR1 Reserved PWM_ 20 0000 PWM CTRL PWM_ 21 0000 PWM 0 FCTRL PWM_ 22 0000 PWM FLTACK PWM_ 23 ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) PWM_ 2C 0FFF PWM 0 DTIM0 PWM_ 2D 0FFF PWM 0 DTIM1 PWM_ 2E FFFF PWM DMAP1 PWM_ 2F 00FF PWM 0 ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) PWM_ 38 0000 PWM FFILT2 PWM_ 39 0000 PWM FFILT3 3B–3F — PWM Reserved INTC_ 40 0000 INTC INT ICSR INTC_ 41 ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) ADC0_ 6A 001F ADC0 0 ADCSC1B ADC0_ 6B 0000 ADC0 0 ADCRA ADC0_ 6C 0000 ADC0 0 ADCRB 6D–6F — ADC0 Reserved ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) PGA0_ A1 0002 PGA0 0 CNTL1 PGA0_ A2 000E PGA0 0 CNTL2 A3 0000 PGA0 PGA0_STS 0 A4–BF — PGA0 Reserved PGA1_ ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) E4 0000 SCI SCI_DATA 0 E5–FF — SCI Reserved SPI_ 00 6141 SPI SPR SCTRL SPI_ 01 000F SPI WOM DSCTRL 02 ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) 28 0000 I2C I2C_SLT1 0 29 0000 I2C I2C_SLT2 0 30–3F — I2C Reserved COP_ 40 0302 COP 0 CTRL COP_ 41 ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) OCCS_ 66 0000 OCCS 0 CLKCHKT OCCS_ 67 0000 OCCS 0 PROT 68–7F — OCCS Reserved GPIOA_ 80 00FF GPIOA 0 PUR ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) 8E–9F — GPIOA Reserved GPIOB_ A0 00FF GPIOB 0 PUR A1 0000 GPIOB GPIOB_DR 0 GPIOB_ A2 0000 GPIOB 0 DDR GPIOB_ ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) C1 0000 GPIOC GPIOC_DR 0 GPIOC_ C2 0000 GPIOC 0 DDR GPIOC_ C3 0080 GPIOC 0 PER C4 — GPIOC Reserved GPIOC_ ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) GPIOD_ E3 0080 GPIOD 0 PER E4 — GPIOD Reserved GPIOD_ E5 0000 GPIOD 0 IENR GPIOD_ E6 0000 GPIOD 0 IPOLR ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) GPIOE_ 05 0000 GPIOE 0 IENR GPIOE_ 06 0000 GPIOE 0 IPOLR GPIOE_ 07 0000 GPIOE 0 IPR GPIOE_ 08 0000 GPIOE ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) GPIOF_ 27 0000 GPIOF 0 IPR GPIOF_ 28 0000 GPIOF 0 IESR 29 — GPIOF Reserved GPIOF_ 2A 0000 GPIOF 0 RAWDATA ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) 46 0000 SIM SIM_PCR 47 0000 SIM SIM_PCE 48 0000 SIM SIM_SDR 49 F000 SIM SIM_ISAL 4A 0000 SIM SIM_PROT 0 4B ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex 00-- PMC PMC_CR2 0 7F — PMC Reserved CMP0_ 80 0000 CMP0 0 CR0 CMP0_ 81 0000 CMP0 0 CR1 ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 14 15 (Hex) (Hex) CMP2_ C2 0000 CMP2 0 FPR CMP2_ C3 0000 CMP2 0 SCR C4–DF — CMP2 Reserved E0 0000 PIT PIT_CTRL 0 E1 ...
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Table 10-41. Detailed Peripheral Memory Map (continued) Offset Reset Bit Addr. Value Periph. Register 15 (Hex) (Hex) FM_ 00 0000 HFM 0 CLKDIV 01 0000 HFM FM_CNFG -000 HFM FM_SECHI FM_ 04 0000 HFM 0 SECLO 06–0F ...
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The binary reset value of this register is FS00 0000 0000 0000, where F indicates that the reset state is loaded from the flash array during reset, and where S indicates that the reset state is determined by the ...
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... Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com MC56F8006 Document Number: Rev. 2 03/2009 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...