mc56f8006 Freescale Semiconductor, Inc, mc56f8006 Datasheet - Page 79

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mc56f8006

Manufacturer Part Number
mc56f8006
Description
Digital Signal Controller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Freescale Semiconductor
1
2
3
Peripheral
Reserved
USER6
Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from
the vector table, providing only 19 bits of address.
If the VBA is set to the reset value, the first two locations of the vector table overlay the chip reset addresses because the
reset address would match the base of this vector table.
USER6 vector can be defined as a fast interrupt if the instruction located in this vector location is not a JSR or BSR instruction.
Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference Manual for detail.
USER1
USER2
USER3
USER4
USER5
GPIOC
GPIOD
GPIOA
GPIOB
GPIOE
GPIOF
SWILP
TMR0
TMR1
RTC
core
core
core
core
PIT
3
Number
Vector
34- 39
24
25
26
27
28
29
30
29
30
33
40
41
42
43
44
45
46
47
48
49
50
0x22-0x27
Encoding
0x1A
0x1B
0x1C
0x1D
0x1E
User
0x18
0x19
0x1F
0x20
0x21
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2
Table 40. Interrupt Vector Table Contents
Priority
Level
-1
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
1
1
1
2
2
2
Vector Base
Address +
P:0x44 -
P:0x3C
P:0x5C
P:0x36
P:0x38
P:0x3A
P:0x3E
P:0x4E
P:0x50
P:0x52
P:0x54
P:0x56
P:0x58
P:0x5A
P:0x5E
P:0x60
P:0x62
P:0x64
P:0x30
P:0x32
P:0x34
P:0x40
P:0x42
User Programmable Priority Level 1 Interrupt
User Programmable Priority Level 1 Interrupt
User Programmable Priority Level 1 Interrupt
User Programmable Priority Level 2 Interrupt
User Programmable Priority Level 2 Interrupt
User Programmable Priority Level 2 Interrupt
Dual Timer, Channel 0 Interrupt
Dual Timer, Channel 1 Interrupt
SW Interrupt Low Priority
Interval Timer Interrupt
1
Interrupt Function
GPIOC Interrupt
GPIOD Interrupt
Real Time Clock
GPIOA Interrupt
GPIOB Interrupt
GPIOE Interrupt
GPIOF Interrupt
SW Interrupt 0
SW Interrupt 1
SW Interrupt 2
SW Interrupt 3
Reserved
Interrupt Vector Table
79

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