cop8cce9imt9 National Semiconductor Corporation, cop8cce9imt9 Datasheet - Page 28

• Manufacturer Part Number: cop8cce9imt9
• Description: 8-bit Cmos Flash Microcontroller With 8k Memory, Virtual Eeprom, 10-bit A/d And Brownout Reset
• Manufacturer: National Semiconductor Corporation

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11.0 In-System Programming
the page should be loaded. For mass erase operations,
0000 must be placed into the address registers. When read-
ing the Option register, FFFF (hex) should be placed into the
address registers. Registers ISPADHI and ISPADLO are
cleared to 00 on Reset. These registers can be loaded from
either flash program memory or Boot ROM and must be
maintained for the entire duration of the operation.
Note: The actual memory address of the Option Register is
0x3FFF (hex), however the MICROWIRE/PLUS ISP routines
require the address FFFF (hex) to be used to read the
Option Register when the Flash Memory is secured.
11.3.2 ISP Read Data Register
The Read Data Register (ISPRD) contains the value read
back from a read operation. This register can be accessed
from either flash program memory or Boot ROM. This regis-
ter is undefined on Reset.
(Continued)
Addr 15 Addr 14
Bit 7
Addr 7
Bit7
Bit 7
Bit 7
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 6
Bit6
Addr 6
Bit 6
Bit 6
TABLE 4. High Byte of ISP Address
TABLE 5. Low Byte of ISP Address
TABLE 6. ISP Read Data Register
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Addr 13
Bit 5
Addr 5
Bit5
Bit 5
Bit 5
Addr 12 Addr 11 Addr 10
Addr 4
Bit 4
Bit 4
Bit 4
Bit4
ISPADLO
ISPADHi
5
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
ISPRD
Bit 3
Addr 3
Bit3
Bit 3
Bit 3
Bit 2
Addr 2
Bit2
Bit 2
Bit 2
4
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
Register Bit
TABLE 8. PGMTIM Register Format
Addr 9
Addr 1
Bit 1
Bit 1
Bit 1
Bit1
3
0
0
0
0
0
0
1
1
1
0
0
1
0
1
1
0
Addr 8
Addr 0
Bit 0
Bit 0
Bit 0
Bit0
PGMTIM
28
2
0
0
0
1
1
1
0
0
1
0
1
1
1
1
1
1
11.3.3 ISP Write Data Register
The Write Data Register (ISPWR) contains the data to be
written into the specified address. This register is undeter-
mined on Reset. This register can be accessed from either
flash program memory or Boot ROM. The Write Data register
must be maintained for the entire duration of the operation.
11.3.4 ISP Write Timing Register
The Write Timing Register (PGMTIM) is used to control the
width of the timing pulses for write and erase operations. The
value to be written into this register is dependent on the
frequency of CKI and is shown in Table 8. This register must
be written before any write or erase operation can take
place. It only needs to be loaded once, for each value of CKI
frequency. This register can be loaded from either flash
program memory or Boot ROM and must be maintained for
the entire duration of the operation. The MICROWIRE/PLUS
ISP routine that is resident in the boot ROM requires that this
Register be defined prior to any access to the Flash memory.
Refer to Section 11.7 MICROWIRE/PLUS ISP for more in-
formation on available ISP commands. On Reset, the PG-
MTIM register is loaded with the value that corresponds to
10 MHz frequency for CKI.
Bit 7
Bit7
Bit 6
Bit6
1
0
1
1
0
0
1
0
1
1
0
1
0
1
1
1
1
TABLE 7. ISP Write Data Register
Bit 5
Bit5
0
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
Bit 4
Bit4
ISPWR
Bit 3
Bit3
CKI Frequency Range
200 kHz–266.67 kHz
500 kHz–666.67 kHz
800 kHz–1.067 MHz
112.5 kHz–150 kHz
62.5 kHz–83.3 kHz
50 kHz–66.67 kHz
100 kHz–133 kHz
150 kHz–200 kHz
225 kHz–300 kHz
300 kHz–400 kHz
375 kHz–500 kHz
600 kHz–800 kHz
1 MHz–1.33 MHz
25 kHz–33.3 kHz
37.5 kHz–50 kHz
75 kHz–100 kHz
Bit 2
Bit2
Bit 1
Bit1
Bit 0
Bit0