cop8tab5 National Semiconductor Corporation, cop8tab5 Datasheet - Page 15

• Manufacturer Part Number: cop8tab5
• Description: 8-bit Cmos Rom Microcontroller With 2k Or 4k Memory
• Manufacturer: National Semiconductor Corporation

10.0 Functional Description
Example: The following sets a value in the Option Register
and User Identification for a COP8TAC9HLQ7. The Option
Register bit values shown select options: Security disabled,
WATCHDOG enabled HALT mode enabled and execution
will commence from ROM Memory.
10.5 RESET
The device is initialized when the RESET pin is pulled low or
the On-chip Power-On Reset is activated.
The following occurs upon initialization:
(Continued)
Port A: TRI-STATE (High Impedance Input)
Port B: TRI-STATE (High Impedance Input)
Port J: Output High
Port L: TRI-STATE (High Impedance Input)
PC: CLEARED to 0000
PSW, CNTRL and ICNTRL registers: CLEARED
SIOR:
ITMR, CLKPS: Cleared
Accumulator and Timer 1:
CWKEN, CWKEDG, LWKEN, LWKEDG: CLEARED
CWKPND, LWKPND: RANDOM
SP (Stack Pointer):
B and X Pointers:
RAM:
Port G: TRI-STATE (High Impedance Input). Exceptions: If
Watchdog is enabled, then G1 is Watchdog output. G0
and G2 have their weak pull-up enabled during RESET.
.chip
.sect
.db
.endsect
...
.end
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
RANDOM after RESET
Initialized to RAM address 06F Hex
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
.endsect
8TAC
option, conf
0x01
start
FIGURE 9. Reset Logic
;wd, halt, flex
;configures
;options
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15
10.5.1 External Reset
The RESET input, when pulled low, initializes the device.
The RESET pin must be held low for a minimum of one
instruction cycle to guarantee a valid reset. An R/C circuit on
the RESET pin with a delay 5 times (5x) greater than the
power supply rise time is recommended. Reset should also
be wide enough to ensure crystal start-up upon Power-Up.
RESET may also be used to cause an exit from the HALT
mode.
A recommended reset circuit for this device is shown in
Figure 10.
10.5.2 On-Chip Power-On Reset
The device generates an internal reset as V
voltage level above 2.0V. The on-chip reset circuitry is able
to detect both fast and slow rise times on V
between 20 µs and 10 ms).
Under no circumstances should the RESET pin be allowed
to float. If the on-chip Power-On Reset feature is being used,
RESET pin should be connected to V
through a pull-up resistor. The output of the power-on reset
detector will always preset the Idle timer to 00FF(256 t
this time, the internal reset will be generated.
The internal reset will not be turned off until the Idle timer
underflows. The internal reset will perform the same func-
tions as external reset. The user is responsible for ensuring
that V
t
Power On Reset circuit will generate no additional internal
resets as long as V
Note: While the POR feature of the COP8TAB5/TAC5 was never intended to
C
. After the underflow, the logic is designed such that the
WATCHDOG (if enabled):
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, with the
WATCHDOG service window bits set and the Clock Moni-
tor bit set. The WATCHDOG and Clock Monitor circuits
are inhibited during reset. The WATCHDOG service win-
dow bits being initialized high default to the maximum
WATCHDOG service window of 64k T0 clock cycles. The
Clock Monitor bit being initialized high will cause a Clock
Monitor error following reset if the clock has not reached
the minimum specified frequency at the termination of
reset. A Clock Monitor error will cause an active low error
output on pin G1. This error output will continue until
16–32 T0 clock cycles following the clock frequency
reaching the minimum specified value, at which time the
G1 output will go high.
FIGURE 10. Reset Circuit Using External Reset
function as a brownout detector, there are certain constraints of this
CC
is at the minimum level for operating within the 256
CC
remains above 2.0V.
CC
, either directly or
CC
20091722
(V
CC
CC
www.national.com
rises to a
rise time
C
). At