scf5250 Freescale Semiconductor, Inc, scf5250 Datasheet - Page 13

• Manufacturer Part Number: scf5250
• Description: Scf5250 Integrated Coldfire Microprocessor Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

4.3.1
4.3.2
This signal indicates during any bus cycle whether a read or write is in progress. A low is write cycle and
a high is a read cycle.
4.3.3
The OE signal is intended to be connected to the output enable of asynchronous memories connected to
chip selects. During bus read cycles, the ColdFire processor will drive OE low.
4.3.4
The data bus (D[31:16]) is bi-directional and non-multiplexed. Data is registered by the SCF5250 on the
rising clock edge. The data bus uses a default configuration if none of the chip-selects or DRAM bank
match the address decode. All 16 bits of the data bus are driven during writes, regardless of port width or
operand size.
4.3.5
The TA/GPIO12 pin is the transfer acknowledge signal.
4.4
The following SDRAM signals provide a glueless interface to external SDRAM. An SDRAM width of 16
bits is supported and can access as much as 32MB of memory. ADRAMs are not supported.
Freescale Semiconductor
•
•
Synchronous DRAM Column Address Strobe The SDCAS/GPIO39 active low pin provides a seamless interface to
Synchronous DRAM row address strobe
The address bus provides the address of the byte or most significant byte of the word or longword
being transferred.The address lines also serve as the DRAM address pins, providing multiplexed
row and column address signals.
Bits 23 down to 1 and 24 of the address are available. A24 is intended to be used with 256 Mbit
DRAM’s. Signals are named:
— A[23:1]
— A20/24
SDRAM Controller Signals
Address Bus
Read-Write Control
Output Enable
Data Bus
Transfer Acknowledge
Synchronous DRAM Write
SDRAM Signal
SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1
Table 4. SDRAM Controller Signals
The SDRAS/GPIO59 active low pin provides a seamless interface to the
RAS input on synchronous DRAM
CAS input on synchronous DRAM.
The SDWE/GPIO38 active-low pin is asserted to signify that a SDRAM
write cycle is underway. This pin outputs logic ‘1’ during read bus cycles.
Description
Signal Descriptions
13