scf5250 Freescale Semiconductor, Inc, scf5250 Datasheet - Page 19

• Manufacturer Part Number: scf5250
• Description: Scf5250 Integrated Coldfire Microprocessor Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

4.17 Crystal Trim
The XTRIM/GPIO0 output produces a pulse-density modulated phase/frequency difference signal to be
used after low-pass filtering to control varicap-voltage to control crystal oscillation frequency. This will
lock the crystal to the incoming digital audio signal.
4.18 Clock Out
The MCLK1/GPIO11 and QSPI_CS2/MCLK2/GPIO24 can serve as DAC clock outputs. When
programmed as DAC clock outputs, these signals are directly derived from the crystal oscillator or clock
Input (CRIN).
4.19 Debug and Test Signals
These signals interface with external I/O to provide processor debug and status signals.
4.19.1 Test Mode
The TEST[2:0] inputs are used for various manufacturing and debug tests. For normal mode TEST [2:1]
should be ways be tied low. TEST0 should be set high for BDM debug mode and set low for JTAG mode.
4.19.2 High Impedance
The assertion of HI_Z will force all output drivers to a high-impedance state. The timing on HI_Z is
independent of the clock.
4.19.3 Processor Clock Output
The internal PLL generates this PSTCLK/GPIO51 and output signal, and is the processor clock output that
is used as the timing reference for the Debug bus timing (DDATA[3:0] and PST[3:0]). The
PSTCLK/GPIO51 is at the same frequency as the core processor.
Freescale Semiconductor
QSPICS1/EBUOUT2/GPIO16
QSPICS0/EBUIN4GPIO15
QSPICS2/MCLK2/GPIO24
CS1/QSPICS3/GPIO28
Serial Module Signal
JTAG operation will override the HI_Z pin.
Table 12. Queued Serial Peripheral Interface (QSPI) Signals (continued)
SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1
4 different QSPI chip selects
NOTE
Description
Signal Descriptions
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