scf5250 Freescale Semiconductor, Inc, scf5250 Datasheet - Page 21

• Manufacturer Part Number: scf5250
• Description: Scf5250 Integrated Coldfire Microprocessor Data Sheet
• Manufacturer: Freescale Semiconductor, Inc

4.20 BDM/JTAG Signals
The SCF5250 complies with the IEEE 1149.1A JTAG testing standard. The JTAG test pins are multiplexed
with background debug pins.
4.21 Clock and Reset signals
These signals configure the SCF5250 and provide interface signals to the external system.
4.21.1 Reset In
Asserting RSTI causes the SCF5250SCF5250 to enter reset exception processing. When RSTI is
recognized, the data bus is tri-stated.
4.21.2 Clock Input
SCF5250 includes on -chip crystal oscillator. The crystal should be connected between CRIN and CROUT.
An externally generated clock signal can also be used and should be connected directly to the CRIN pin.
4.22 Wake-Up Signal
To exit power down mode, apply a LOW level to the WAKE_UP/GPIO21 input pin.
4.23 On-chip Linear Regulator
The SCF5250 includes an on-chip linear regulator. This regulator provides an 1.2 V output which is
intended to be used to power the SCF5250 core. Three pins are associated with this function.
LININ, LINOUT and LINGND. Typically LININ would be fed by the I/O (PAD) supply (3.3 V) with
separate filtering recommended to provide some isolation between the I/O and the core.
In portable solutions this linear regulator may not be efficient enough and in this case we would expect the
1.2 V supply to be generated externally, possibly by a highly efficient DC-DC convertor.
If not used leave pins not connected.
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Freescale Semiconductor
Electrical Characteristics
Supply Core Voltage
Maximum Core Operating Voltage
Minimum Core Operating Voltage
SCF5250 Integrated ColdFire® Microprocessor Data Sheet, Rev. 1.1
Rating
Table 14. Maximum Ratings
Symbol
V
V
V
cc
cc
cc
-0.5 to +2.5
Value
+1.32
+1.08
Electrical Characteristics
Units
V
V
V
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