msp430f2121irge Microchip Technology Inc., msp430f2121irge Datasheet - Page 2

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msp430f2121irge

Manufacturer Part Number
msp430f2121irge
Description
Msp430
Manufacturer
Microchip Technology Inc.
Datasheet

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MSP430x21x1
MIXED SIGNAL MICROCONTROLLER
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
device pinout
functional block diagram
2
P2.2/CAOUT/TA0/CA4
P2.1/INCLK/CA3
XOUT/P2.7/CA7
P2.0/ACLK/CA2
XIN/P2.6/CA6
NOTE: See port schematics section for detailed I/O information.
P2.5/CA5
RST/NMI
TEST
V SS
V CC
DW, PW, or DGV PACKAGE
1
2
3
4
5
6
7
8
9
10
XIN
Basic Clock
(TOP VIEW)
Emulation
Registers
System+
Interface
16MHz
incl. 16
(2BP)
JTAG
CPU
MCLK
XOUT
ACLK
SMCLK
20
19
18
17
16
15
14
13
12
11
POST OFFICE BOX 655303
MAB
MDB
Protection
Brownout
RST/NMI
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/TA2/CA1
P2.3/TA1/CA0
Flash
VCC
8kB
4kB
2kB
1kB
VSS
RAM
256B
256B
128B
128B
DALLAS, TEXAS 75265
XOUT/P2.7/CA7
P2.0/ACLK/CA2
Comparator
8 Channel
Input Mux
Watchdog
15/16− Bit
XIN/P2.6/CA6
WDT+
_A+
RST/NMI
Note: NC pins not internally connected
P1.x & JTAG
pull− up/down
V SS
capability,
Timer_A3
NC
Registers
Interrupt
resistors
Port P1
8 I/O
3 CC
Power Pad connection to V SS recommended
8
1
2
3
4
5
6
24 23 22 21 20
RGE PACKAGE
7
pull− up/down
(TOP VIEW)
XIN/XOUT
capability,
8
resistors
Interrupt
Port P2
P2.x &
8 I/O
9
8
10
11
12
19
18
17
16
15
14
13
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK

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