sc68c752b NXP Semiconductors, sc68c752b Datasheet - Page 15

• Manufacturer Part Number: sc68c752b
• Description: 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. , With 64-byte Fifos And Motorola Up Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
SC68C752B_3
Product data sheet
6.5.1 Interrupt mode operation
6.5.2 Polled mode operation
In Interrupt mode (if any bit of IER[3:0] is 1) the processor is informed of the status of the
receiver and transmitter by an interrupt signal, IRQ. Therefore, it is not necessary to
continuously poll the Line Status Register (LSR) to see if any interrupt needs to be
serviced.
In Polled mode (IER[3:0] = 0000) the status of the receiver and transmitter can be
checked by polling the Line Status Register (LSR). This mode is an alternative to the FIFO
Interrupt mode of operation where the status of the receiver and transmitter is
automatically known by means of interrupts sent to the CPU.
Polled mode operation.
Fig 8. Interrupt mode operation
Fig 9. FIFO Polled mode operation
Figure 8
PROCESSOR
PROCESSOR
shows Interrupt mode operation.
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 03 — 29 November 2005
R/W
R/W
IRQ
THR
THR
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
IER
IER
IIR
IIR
Figure 9
1
0
SC68C752B
1
0
RHR
RHR
1
002aab096
0
002aab097
shows FIFO
1
0
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