sc68c752b NXP Semiconductors, sc68c752b Datasheet - Page 23

• Manufacturer Part Number: sc68c752b
• Description: 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. , With 64-byte Fifos And Motorola Up Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
SC68C752B_3
Product data sheet
7.3 FIFO Control Register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels, and selecting the type of DMA signalling.
shows FIFO Control Register bit settings.
Table 12:
Bit
7:6
5:4
3
2
1
0
Symbol
FCR[7] (MSB),
FCR[6] (LSB)
FCR[5] (MSB),
FCR[4] (LSB)
FCR[3]
FCR[2]
FCR[1]
FCR[0]
FIFO Control Register bits description
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 03 — 29 November 2005
Description
RX trigger. Sets the trigger level for the RX FIFO.
TX trigger. Sets the trigger level for the TX FIFO.
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
DMA mode select.
Reset TX FIFO.
Reset RX FIFO.
FIFO enable.
00 - 8 characters
01 - 16 characters
10 - 56 characters
11 - 60 characters
00 - 8 spaces
01 - 16 spaces
10 - 32 spaces
11 - 56 spaces
logic 0 = Set DMA mode ‘0’
logic 1 = Set DMA mode ‘1’
logic 0 = No FIFO transmit reset (normal default condition)
logic 1 = Clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC68C752B
Table 12
23 of 49