lf3321qc9 LOGIC Devices Incorporated, lf3321qc9 Datasheet - Page 17

• Manufacturer Part Number: lf3321qc9
• Description: Horizontal Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
Matrix-vector
Multiply Mode
Continued
LOGIC Devices Incorporated
Operating Modes
To configure the LF3321 for matrix-vector multiplication, bit 4 of Configuration Register 5 must be set to
1 (Table 7). The configuration for single filter mode or dual filter mode will still apply. Writing 012H or
016H to Configuration Register 5 will configure the device for dual filter mode, [8x8][8x1] matrix-vector
multiplication. Subsequently, writing 014H to Configuration Register 5 will configure the device for single
filter mode, [16x16][16x1] matrix-vector multiplication.
Some functions of the LF3321 must be disabled when configured for matrix-vector multiplication. This
will apply to both the single filter mode and the dual filter mode; these functions are data reversal and
interleave/decimation. The LF3321 can be cascaded to realize larger matrices.
Data reversal can be disabled by setting bit 6, of Configuration Register 1 (Filter A) and Configuration
Register 3 (Filter B), both to 1. The Odd-Tap, interleave mode will need to be disabled. Writing a 0 to bit 0
of Configuration Register 1 and Configuration Register 3 will disable the odd-tap interleave mode for Filter
A and Filter B. When data is not being interleaved or decimated, the I/D Register length should be set to a
length of one (Table 3 and Table 5). Therefore, writing 040H to Configuration Register 1 and 3 will disable
the data reversal and set the corresponding inherent characteristics for the desired matrix function.
The Filter A ALU and Filter B ALU are to be configured for A+B (Table 2 and Table 4); so that condition
A+0 is satisfied. To accomplish this, bit 0 is to be reset to 0, bit 1 is to be set to 1, and bit 2 is to be reset
to 0. Writing 002H to Configuration Register 0 (Filter A) and Configuration Register 2 (Filter B) will set the
corresponding registers to satisfy the A+0 condition.
The timing diagrams in Figure 19 and 20 will assume that the Configuration Registers, the coefficient sets,
and the first set of data values (data set) have been loaded. Loading input data for an [8x8][8x1] matrix
operation requires 9 clock cycles and loading input data for a [16x16][16x1] matrix operation requires 17
clock cycles. When configured for an [8x8][8x1] matrix-vector operation, 8 data values are required for
loading. When configured for a [16x16][16x1] matrix-vector operation, 16 data values are required for
loading. Each data value is fed through the I/D Registers, using the corresponding input. Once the final
data value, of the data set, has been loaded TXFRA/TXFRB should be brought LOW for one clock cycle to
complete the loading. Once this occurs, the data set is then bank loaded into the respective registers ready
to begin the matrix-vector multiplication operation. The current data set will not change until TXFRA/TXFRB
is brought LOW again. To satisfy the matrix equation (see Figure 18), the current data set is held for the
duration of the required matrix dimension while cycling through each coefficient set (CENA/CENB must
be held LOW). During this time new data values can be loaded serially, ready for the next activation of
TXFRA/TXFRB. To insure the correct evaluation of the matrix-vector multiplication equation, it is imperative
that the coefficient values are paired with their corresponding data values.
For the [8x8][8x1] matrix-vector configuration (dual filter mode), the first result will appear 19 clock cycles
from the first data input, DIN15-0 (Filter A) and RIN15-0 (Filter B); device latency for the first result is 10
clock cycles (10+9 = 19).
Figure 17. Matrix-vector Multiply Mode
N
TXFRA
TXFRB
COEF (N-1)
COEF 2
COEF 1
COEF 0
DIN
RIN
11-0
11-0
12
Dual Filter Mode, N=8
Single FIlter Mode, N=16
12
12
12
12
17
A
ALU
0
B
N
A
ALU
0
B
32
A
ALU
Horizontal Digital Image Filter
B
0
A
ALU
Improved Performance
B
0
Video Imaging Products
Feb 5, 2003 LDS.3321-A
LF3321