lf3321qc9 LOGIC Devices Incorporated, lf3321qc9 Datasheet - Page 18

• Manufacturer Part Number: lf3321qc9
• Description: Horizontal Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
Matrix-vector
Multiply Mode
Continued
LOGIC Devices Incorporated
Operating Modes
The result will appear at the corresponding filter output, DOUT15-0 (Filter A) and ROUT3-0/COUT11-0
(Filter B). For the [16x16][16x1] matrix-vector configuration (single filter mode), the first result will appear 28
clock cycles from the first data input, DIN15-0; device latency for the first result is 11 clock cycles (11+17 =
28). The result will appear at the corresponding filter output, DOUT15-0. Subsequently, for both dual and
single filter mode configurations, the sum of products will continue to appear every clock cycle thereafter
until the matrix dimension has been realized. The total pipeline latency for a complete [8x8][8x1] matrix-
vector operation is 26 clock cycles and the total pipeline latency for a complete [16x16][16x1] matrix-vector
operation is 43 clock cycles. Therefore, to process two square matrices simultaneoulsy, of size N=8, a total
of 73 clock cycles are all that is required. Similarly, to process a single square matrix, of size N=16, a
total of 283 clock cycles are required.
Once again, the timing diagrams (see Figure 19 and 20) will assume that the Configuration Registers,
the coefficient sets, and the data values have been loaded. The corresponding timing diagram loading
sequence for the coefficient banks and Configuration/Control registers are included in the LF3321 data
sheets (Figure 9 and Figure 10 respectively). Further reference to timing diagram loading sequence for the
RSL registers are also included in the device data sheet (Figure 14, Figure 13, and Figure 12). The Filter
A and Filter B LF Interface
and coefficient banks.
The Matrix Multiplication Mode is valid in the Double Wide Data/Coefficient Mode. However, there are some
special considerations when this mode is desired. The LF3321 must be configured for single filter mode
only, for a maximum (8x8) matrix. The user must disable the cascaded filter mode, the accumulator access
mode, and the data reversal (see Table 7).
ROUT
Figure 18. Matrix Equation
SHENA / SHENB
Figure 19. Dual Filter, Matrix Multiply Timing Sequence
TXFRA/ TXFRB
CENA / CENB
3-0
/COUT
DOUT
DIN
RIN
CAA
CAB
CLK
11-0
11-0
15-0
15-0
7-0
7-0
*
**
***
8 Clocks - End of First Data/Coefficient Set
10 Clocks - First Output of First Data/Coefficient Set
17 Clocks - Final Output of First Data/Coefficient Set
TM
CF
1
Data Set 1 with 8 Coefficient Sets
00
are used to load data into the Filter A and Filter B Configuration Registers
DATA SET 0
CF
2
01
CF
3
18
02
R
R
R
R
0
1
2
i
=
C
C
C
C
C = COEFFICIENTS
D = DATA INPUT
R = DATA OUTPUT
00
10
20
i0
CF
R
C
C
C
C
8*
i
For j=0,1,2,...,(N-1)
07
01
11
21
i1
=
N=8 or 16
C
C
C
C
(N-1)
i=0
02
12
22
i2
CF
9
Data Set 2 with 8 Coefficient Sets
C
10
ij
C
C
C
C
D
DATA SET 1
0j
1j
2j
ij
i
CF
10**
OUT 0
11
Horizontal Digital Image Filter
D
D
D
D
0
1
2
i
CF
11
OUT 1
12
Improved Performance
Video Imaging Products
CF
17***
OUT 7
17
CF
18
OUT 0
20
Feb 5, 2003 LDS.3321-A
CF
OUT 1
21
LF3321