xr16m564 Exar Corporation, xr16m564 Datasheet - Page 30
![no-image](/images/manufacturer_photos/0/2/243/exar_corporation_sml.jpg)
xr16m564
Manufacturer Part Number
xr16m564
Description
1.62v To 3.63v Quad Uart With 32-byte Fifo
Manufacturer
Exar Corporation
Datasheet
1.XR16M564.pdf
(55 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
xr16m564DIV64-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Company:
Part Number:
xr16m564IJ68-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Company:
Part Number:
xr16m564IV64-F
Manufacturer:
EXAR
Quantity:
5 000
Company:
Part Number:
xr16m564IV64-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
xr16m564IV64-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
Company:
Part Number:
xr16m564IV80-F
Manufacturer:
Exar Corporation
Quantity:
10 000
XR16M564/564D
1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•
•
FCR[3]: DMA Mode Select
Controls the behavior of the -TXRDY and -RXRDY pins. See DMA operation section for details.
•
•
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4 = 1)
(logic 0 = default, TX trigger level = one)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
T
ABLE
B
FCR
IT
0
0
1
1
12: T
-7
RANSMIT AND
B
FCR
IT
0
1
0
1
-6
B
FCR
IT
0
0
1
1
-5
R
ECEIVE
BIT
FCR
0
1
0
1
-4
30
FIFO T
Table 12
T
R
RIGGER
L
ECEIVE
EVEL
RIGGER
16
24
30
8
Table 12
below shows the selections.
L
EVEL
T
T
RANSMIT
L
RIGGER
shows the complete selections.
EVEL
16
24
30
S
8
ELECTION
REV. 1.0.0