xr16m752im48 Exar Corporation, xr16m752im48 Datasheet - Page 31

• Manufacturer Part Number: xr16m752im48
• Description: Xr68m752 -high Performance Duart With 64-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.2
MCR[2]: OP1# / FIFO Rdy Enable
OP1# is not available as an output pin on the M752. But it is available for use during Internal Loopback Mode
(MCR[4] = 1). In the Internal Loopback Mode, this bit is used to write the state of the modem RI# interface
signal.
This bit is also used to select between the SPR, TLR and FIFO Rdy registers. All of these registers are
accessible at address offset 0x7 when LCR
MCR[3]: OP2# Output / INT Output Enable
This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used
as a general purpose output.
•
•
MCR[4]: Internal Loopback Enable
•
•
MCR[5]: Xon-Any Enable (requires EFR bit-4=1 to write to this bit)
•
•
MCR[6]: TCR and TLR Enable (requires EFR bit-4=1 to write to this bit)
This bit enables the TCR and TLR registers at address offset 0x6 and 0x7, respectively. See
for the correct register setting to access the TLR register. See
TCR register.
•
•
Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default).
Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Logic 0 = Disable Xon-Any function (default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the M752 is programmed to use the Xon/Xoff flow control.
Logic 0 = Reserved (default).
Logic 1 = Enable access to the TCR and TLR registers.
EFR[4] MCR[6] MCR[4, 2] Register at Address Offset 0x7
X
0
1
1
EFR[4] MCR[6] Register at Address Offset 0x6
0
1
1
T
T
X
X
0
1
ABLE
ABLE
X
0
1
12: R
13: R
≠ ’01’
≠ ’01’
≠ ’01’
=’01’
≠ 0xBF
Modem Status Register (MSR)
Modem Status Register (MSR)
Trigger Control Register (TCR)
EGISTER AT
EGISTER AT
. However, LCR = 0xBF is required to access EFR.
Scratchpad Register (SPR)
Scratchpad Register (SPR)
Trigger Level Register (TLR)
FIFO Ready Register (FIFO Rdy)
31
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
A
A
DDRESS
DDRESS
Table 13
O
O
Figure
FFSET
FFSET
0
0
below for the setting to access the
12.
X
X
7
6
XR16M752/XR68M752
Table 12
above