XR16M752 EXAR [Exar Corporation], XR16M752 Datasheet
XR16M752
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XR16M752 Summary of contents
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... Covered by U.S. Patent #5,649,122 OTE APPLICATIONS • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls F 1. XR16M752 B D IGURE LOCK IAGRAM A2:A0 D7:D0 IOR# (NC) IOW# (R/W#) CSA# (CS#) CSB# (A3) 8-bit Data INTA (IRQ#) Bus ...
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... RXRDYA # 5 TXA TXB 6 30 IRQ GND 2 REV. 1.0.2 24 RESET 23 RTSA# 22 INTA XR16M752 21 INTB 32-pin QFN 20 A0 Intel Mode Only RESET 23 RTSA# 22 INTA XR68M752 INTB 21 32-pin QFN 20 A0 Intel Mode VCC ...
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... When 16/68# pin is HIGH, this input is chip select B (active low) to enable channel B in the device. When 16/68# pin is LOW, this input becomes address line A3 which is used for channel selection in the Motorola bus interface. Input logic 0 selects channel A and logic 1 selects channel B. 3 XR16M752/XR68M752 ANGE EVICE ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Pin Description 32-QFN 48-TQFP N AME INTA (IRQ#) INTB 21 29 (NC) TXRDYA RXRDYA TXRDYB RXRDYB MODEM OR SERIAL I/O INTERFACE TXA 5 7 RXA 4 5 RTSA YPE ESCRIPTION O When 16/68# pin is HIGH for Intel bus interface, this output becomes channel A interrupt output ...
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... This input should be connected to VCC or GND when not used. I UART channel B Carrier-Detect (active low) or general purpose input. This input should be connected to VCC or GND when not used. I UART channel B Ring-Indicator (active low) or general purpose input. This input should be connected to VCC or GND when not used. 5 XR16M752/XR68M752 ...
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... O Crystal or buffered clock output. I Intel or Motorola Bus Select (internal pull-up resistor). This pin is not available for the XR16M752. This pin is available for the XR68M752 only. When 16/68# pin is HIGH Intel Mode, the device will operate in the Intel bus type of interface. When 16/68# pin is LOW Motorola mode, the device will operate in the Motorola bus type of interface ...
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... FIFO trigger levels, infrared encoder and decoder (IrDA ver 1.0), programmable fractional baud rate generator with a prescaler of divide and data rate Mbps with 4X sampling clock rate. The XR16M752 is a 1.62V to 3.63V device. The M752 is fabricated with an advanced CMOS process. Enhanced Features The M752 DUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of 16 bytes in the industry standard 16C550 ...
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... The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The XR16M752 data interface supports the Intel compatible types of CPUs while the XR68M752 supports both the Intel and Motorola compatible data interfaces. No clock (oscillator nor external clock) is required to operate a data bus transaction ...
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... HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Table HANNEL AND ELECT IN CSB# F UNCTION 1 UART de-selected 1 Channel A selected 0 Channel B selected 0 Channel A and B selected HANNEL AND ELECT UNCTION N/A UART de-selected 0 Channel A selected 1 Channel B selected 9 XR16M752/XR68M752 1. ODE ODE “Section 3.0, UART Internal ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.5 DMA Mode The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of the RXRDY# A/B and TXRDY# A/B output pins ...
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... R2 500 ΚΩ − 1 ΜΩ 1.8432 MHz MHz C1 C2 22-47 pF 22-47 pF Figure 16 - 0.0625) in increments of 0.0625 (1/16) to 1/16 whenever the DLD is non-zero and is an odd number. ± 11 XR16M752/XR68M752 ““Section 2.8, 11.” 4). The programmable Baud Table 6 shows the Table sampling rate, these ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO When using 4X sampling mode, the bit time will have a jitter of When using a non-standard data rate crystal or external clock, the divisor value can be calculated multiple of 4. with the following equation(s): Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’ ...
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... XR16M752/XR68M752 16X S AMPLING DLD ROGRAM ROGRAM ATA RROR (HEX) V (HEX) R (%) ALUE ATE ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.9.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s) ...
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... R eceive Tags in D ata B yte LS R bits and E rrors 4:2 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO -FIFO M ODE R eceive D ata S hift D ata Bit R egister ( alidation R eceive D ata H olding R egister Interrupt (ISR bit- XR16M752/XR68M752 R eceive D ata C haracters R XFIFO 1 ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO IGURE ECEIVER PERATION IN 16X Clock ( DLD[5:4] ) Receive Data Shift Register (RSR) 64 bytes by 11-bit wide FIFO Data FIFO Receive Data Byte and Errors 2.11 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission ...
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... RXA TXB RTSA# CTSB# TXA RXB CTSA# RTSB# ON OFF 7 ON OFF 8 Restart 6 Suspend 9 RTS High RTS Low 5 Threshold Threshold 17 XR16M752/XR68M752 Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level FIFO 12 Trigger Level RTSCTS1 ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.15 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the M752 will halt transmission (TX) as soon as the current character has completed transmission ...
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... HIGH PERFORMANCE DUART WITH 64-BYTE FIFO RANSMIT ATA NCODING AND Character Data Bits Bit Time 3/16 Bit Time Bit Time 1/16 Clock Delay Data Bits Character 19 XR16M752/XR68M752 D D ECEIVE ATA ECODING 1 1/2 Bit Time IrEncoder IRdecoder- ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and modem input lines remain steady when the M752 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical Characteristics on page 38 ...
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... HIGH PERFORMANCE DUART WITH 64-BYTE FIFO ACK IN HANNEL AND VCC (THR/FIFO) MCR bit-4=1 (RHR/FIFO) VCC RTS# CTS# VCC DTR# DSR# OP1# RI# VCC OP2# CD# 21 XR16M752/XR68M752 TXA/TXB RXA/RXB RTSA#/RTSB# CTSA#/CTSB# DTRA#/DTRB# DSRA#/DSRB# RIA#/RIB# OP2A#/OP2B# CDA#/CDB# ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 3.0 UART INTERNAL REGISTERS Each of the UART channel in the M752 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting the channel. The complete register set is shown on Table UART CHANNEL A AND B UART INTERNAL REGISTERS ...
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... Bit-5 Bit-4 Bit-3 Resume Resume Halt Bit-2 Bit-1 Bit-0 Bit-3 RX Trig RX Trig TX Trig Bit-2 Bit-1 Bit-0 Bit FIFO RX FIFO 0 B Status A Status 23 XR16M752/XR68M752 EFR B -4 OMMENT Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 RX Line TX RX Data Stat ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T 8: INTERNAL REGISTERS DESCRIPTION. ABLE EAD DDRESS AME RITE A2- DLL RD/WR Bit DLM RD/WR Bit DLD RD/WR IR Mode RS485 Direction Control EFR RD/WR Auto Auto RTS CTS Enable Enable XON1 RD/WR ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M752 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the RTS# interrupt (default). • Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition from low to high. ...
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... LSR (Receiver Line Status Register RXRDY (Receive Data Time-out RXRDY (Received Data Ready TXRDY (Transmit Ready MSR (Modem Status Register RXRDY (Received Xoff or Special character CTS#, RTS# change of state None (default) 27 XR16M752/XR68M752 L EVEL S OURCE OF INTERRUPT Table 9). ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO FCR[1]: RX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic receive FIFO reset (default) • Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not cleared or altered) ...
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... Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format. HIGH PERFORMANCE DUART WITH 64-BYTE FIFO BIT-0 W ORD LENGTH (default TOP BIT LENGTH ORD ( LENGTH IT TIME S 5,6,7 1-1/2 6,7,8 2 (default) 29 XR16M752/XR68M752 ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. • ...
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... Trigger Level Register (TLR) =’01’ FIFO Ready Register (FIFO Rdy) Figure Table 13 13 EGISTER AT DDRESS FFSET X Modem Status Register (MSR) 0 Modem Status Register (MSR) 1 Trigger Control Register (TCR) 31 XR16M752/XR68M752 12. Table 12 above below for the setting to access the ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO MCR[7]: Clock Prescaler Select (requires EFR bit-4=1 to write to this bit) • Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable Baud Rate Generator without further modification, i.e., divide by one (default). ...
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... MSR[7]: CD Input Status Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 33 ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 4.10 Scratch Pad Register (SPR) - Read/Write This is a 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle. There are also two other registers (TLR and FIFO Rdy) that share the same address location as the Scratch Pad Register ...
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... X X Transmit Xon1, Xoff1 X X Transmit Xon2, Xoff2 X X Transmit Xon1 and Xon2, Xoff1 and Xoff2 receive flow control 1 0 Receiver compares Xon1, Xoff1 35 XR16M752/XR68M752 S R AMPLING ATE 16X 8X 4X SEE”INFRARED MODE” ECEIVE OFTWARE LOW ONTROL ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T ABLE EFR -3 EFR -2 EFR BIT BIT ONT ONT EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 5-7, TCR, TLR and DLD to be modified ...
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... Bits 7-0 = 0x00. Only resets to these values during a power up. They do not reset when the Reset Pin is asserted. XOFF2 Bits 7-0 = 0x00. Only resets to these values during a power up. They do not reset when the Reset Pin is asserted. XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO RESET STATE 37 ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T 16: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS I/O SIGNALS TX HIGH OP2# HIGH RTS# HIGH DTR# HIGH RXRDY# HIGH TXRDY# LOW INT Three-State Condition 5.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin ...
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... C, Vcc=1.62 - 3.63V load where applicable L IMITS 1.8V ± 10% 2.5V ± 10 XR16M752/XR68M752 IMITS 3. NITS ONDITIONS -400 -200 uA OH ±10 uA ± XTAL1 = 2 MHz 15 ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AC ELECTRICAL CHARACTERISTICS o Unless otherwise noted: TA=- YMBOL ARAMETER T Data Hold Time (16 mode Address Setup (68 Mode) ADS T Address Hold (68 Mode) ADH T R/W# Setup to CS# (68 Mode) RWS T Read Data Access (68 mode) RDA T Read Data Disable (68 mode) ...
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... RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI# HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T ECLK T ECH & B IMING OR HANNELS Change of state Change of state Active T Active 41 XR16M752/XR68M752 T ECL Change of state Active Active RSI Active Active Change of state ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 15 IGURE ODE NTEL ATA A0-A2 Valid Address T AS CSA#/ CSB# IOR# T RDV D0- IGURE ODE NTEL ATA A0-A2 Valid Address T AS CSA#/ CSB# IOW# D0- EAD IMING ...
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... HIGH PERFORMANCE DUART WITH 64-BYTE FIFO ATA US EAD IMING T T CSL ADH T CSD T RWH T RDH Valid Data ATA US RITE IMING T T CSL ADH T CSD T RWH T WDH T WDS Valid Data 43 XR16M752/XR68M752 Valid Address Valid Data 68Read Valid Address Valid Data 68Write ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 19 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY ...
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... SSI RX FIFO fills Trigger Level or RX Data Timeout T [FIFO M , DMA E IMING ODE NABLED D0:D7 D0:D7 D0: SSI T SSR 45 XR16M752/XR68M752 ] C A & B FOR HANNELS D0:D7 D0: FIFO drops below RX Trigger Level FIFO Empties T T RRI RR RXINTDMA & B FOR HANNELS ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 23 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up Data in TX FIFO TXRDY IOW# (Loading data into FIFO) *INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level. ...
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... INCHES MILLIMETERS MIN MAX MIN 0.039 0.047 1.00 0.002 0.006 0.05 0.037 0.041 0.95 0.007 0.011 0.17 0.004 0.008 0.09 0.346 0.362 8.80 0.272 0.280 6.90 0.020 BSC 0.50 BSC 0.018 0.030 0.45 0 ° 7 ° 0 ° 47 XR16M752/XR68M752 α L MAX 1.20 0.15 1.05 0.27 0.20 9.20 7.10 0.75 7 ° ...
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... XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.193 0.201 4.90 0.138 0.150 3.50 0.007 ...
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... Copyright 2007 EXAR Corporation Datasheet May 2007. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO D ESCRIPTION NOTICE ...
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... IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT ................................................................................................................................ 3 ORDERING INFORMATION PIN DESCRIPTIONS ........................................................................................................ 3 1.0 PRODUCT DESCRIPTION....................................................................................................................... 7 2.0 FUNCTIONAL DESCRIPTIONS............................................................................................................... 8 2.1 CPU INTERFACE................................................................................................................................................. XR16M752/XR68M752 D IGURE ATA 2.2 DEVICE RESET ................................................................................................................................................... 9 2.3 CHANNEL A AND B SELECTION....................................................................................................................... ABLE HANNEL AND ELECT ABLE HANNEL AND ELECT IN 2 ...
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... DMA M D IMING ODE ODE ISABLED T [FIFO M , DMA M E IMING ODE ODE NABLED - .................................................................................. 0.9 ) ............................................................................... XR16M752/XR68M752 A & B ......................................................... 44 A & B ....................................................... & B........................................ 45 HANNELS C A & B......................................... 45 HANNELS ] C A & B ........................... 46 FOR HANNELS ] C A & B ............................ 46 FOR HANNELS I ...