xr16v2650im Exar Corporation, xr16v2650im Datasheet - Page 29
![no-image](/images/manufacturer_photos/0/2/243/exar_corporation_sml.jpg)
xr16v2650im
Manufacturer Part Number
xr16v2650im
Description
High Performance Duart With 32-byte Fifo
Manufacturer
Exar Corporation
Datasheet
1.XR16V2650IM.pdf
(47 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
xr16v2650im-F
Manufacturer:
Exar Corporation
Quantity:
10 000
REV. 1.0.2
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space", LOW state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
•
•
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL, DLM and DLD) enable.
•
•
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
•
•
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
•
•
MCR[2]: IrDA RX Inversion or OP1# (legacy term)
When Infrared mode is enabled (MCR[6]=1 and EFR[4]=1), this bit selects the idle state of the encoded IrDA
data. In internal loopback mode, this bit functions like the OP1# in the 16C550.
•
•
In the Internal Loopback Mode, this bit controls the state of the modem input RI# bit in the MSR register as
shown in
MCR[3]: OP2# Output / INT Output Enable
This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used
as a general purpose output.
•
•
MCR[4]: Internal Loopback Enable
•
•
4.7
Logic 0 = No TX break condition (default).
Logic 1 = Forces the transmitter output (TX) to a “space”, LOW, for alerting the remote receiver of a line
break condition.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
Logic 0 = Force DTR# output HIGH (default).
Logic 1 = Force DTR# output LOW.
Logic 0 = Force RTS# HIGH (default).
Logic 1 = Force RTS# LOW.
Logic 0 = Select RX input as active-low encoded IrDA data (Idle state will be low) (default).
Logic 1 = Select RX input as active-high encoded IrDA data (Idle state will be high).
Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default).
Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set LOW.
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
Figure
12.
29
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
Figure
12.
XR16V2650