xr16v554 Exar Corporation, xr16v554 Datasheet - Page 14
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xr16v554
Manufacturer Part Number
xr16v554
Description
2.25v To 3.6v Quad Uart With 16-byte Fifo
Manufacturer
Exar Corporation
Datasheet
1.XR16V554.pdf
(45 pages)
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XR16V554/554D
2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO
F
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
sampling clock. A bit time is 16X clock periods. The transmitter sends the start-bit followed by the number of
data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are
reported in the Line Status Register (LSR bit-5 and bit-6).
2.9
IGURE
O
UTPUT
MCR Bit-7=0
6. B
153.6k
230.4k
460.8k
921.6k
Transmitter
19.2k
38.4k
76.8k
2400
4800
9600
400
Data Rate
AUD
T
ABLE
R
XTAL1
XTAL2
ATE
6: T
G
Clock (Decimal)
D
ENERATOR
YPICAL DATA RATES WITH A
IVISOR FOR
2304
384
192
Crystal
Buffer
96
48
24
12
Osc /
6
4
2
1
16x
Channels
To Other
D
IVISOR FOR
Clock (HEX)
900
180
C0
0C
60
30
18
06
04
02
01
14.7456 MH
Rate Generator Logic
Programmable Baud
14
16x
DLL and DLM
Registers
DLM P
V
Z CRYSTAL OR EXTERNAL CLOCK
ALUE
09
01
00
00
00
00
00
00
00
00
00
ROGRAM
(HEX)
16 X Sampling
and Receiver
to Transmitter
Rate Clock
DLL P
V
ALUE
C0
0C
00
80
60
30
18
06
04
02
01
ROGRAM
(HEX)
D
E
ATA
RROR
REV. 1.0.2
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)