xr16v554 Exar Corporation, xr16v554 Datasheet - Page 22

• Manufacturer Part Number: xr16v554
• Description: 2.25v To 3.6v Quad Uart With 16-byte Fifo
• Manufacturer: Exar Corporation

XR16V554/554D
2.25V TO 3.6V QUAD UART WITH 16-BYTE FIFO
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
associated with each of these interrupt levels.
•
•
•
•
•
•
•
•
•
•
]
ISR[0]: Interrupt Status
•
•
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source
ISR[4]: Reserved
ISR[5]: Reserved
4.4
4.4.1
4.4.2
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY Data Ready is by RX trigger level.
RXRDY Data Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX FIFO empty.
MSR is by any of the MSR bits 0, 1, 2 and 3.
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending (default condition).
P
L
RIORITY
EVEL
1
2
3
4
5
-
Interrupt Status Register (ISR)
Interrupt Generation:
Interrupt Clearing:
Table
B
IT
0
1
0
0
0
0
-3
9, shows the data values (bit 0-3) for the interrupt priority levels and the interrupt sources
ISR R
B
IT
1
1
1
0
0
0
EGISTER
-2
T
ABLE
S
B
TATUS
IT
1
0
0
1
0
0
9: I
-1
NTERRUPT
B
ITS
B
IT
0
0
0
0
0
1
-0
S
OURCE AND
22
LSR (Receiver Line Status Register)
RXRDY (Receive Data Time-out)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
None (default)
P
RIORITY
S
L
OURCE OF INTERRUPT
EVEL
REV. 1.0.2
Table
9).