xr16v654 Exar Corporation, xr16v654 Datasheet - Page 16

• Manufacturer Part Number: xr16v654
• Description: 2.25v To 3.6v Quad Uart With 64-byte Fifo
• Manufacturer: Exar Corporation

XR16V654/654D
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
the value of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be
programmed during initialization to the operating data rate. The DLL and DLM registers provide the integer part
of the divisor and the DLD register provides the fractional part of the divisor. Only the four lower bits of the DLD
are implemented and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting
1111). Programming the Baud Rate Generator Registers DLL, DLM and DLD provides the capability for
selecting the operating data rate.
external clock at 16X clock rate. If the pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times
less than that shown in
they would quadruple. Also, when using 8X sampling mode, please note that the bit-time will have a jitter (+/- 1/
16) whenever the DLD is non-zero and is an odd number. When using a non-standard data rate crystal or
external clock, the divisor value can be calculated with the following equation(s):
The closest divisor that is obtainable in the V654 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
F
IGURE
Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
7. B
AUD
XTAL2
XTAL1
R
ATE
G
Table
ENERATOR
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
Crystal
Buffer
6. At 8X sampling rate, these data rates would double. And at 4X sampling rate,
Osc/
Table 6
Channels
To Other
DLL = TRUNC(Required Divisor) & 0xFF
DLM = TRUNC(Required Divisor) >> 8
shows the standard data rates available with a 24MHz crystal or
Divide by 4
Divide by 1
Prescaler
Prescaler
16
MCR Bit-7=0
MCR Bit-7=1
(default)
DLL, DLM and DLD
Fractional Baud
Rate Generator
Registers
Logic
16X or 8X or 4X
and Receiver
to Transmitter
Rate Clock
Sampling
REV. 1.0.1