xr16v654 Exar Corporation, xr16v654 Datasheet - Page 28

• Manufacturer Part Number: xr16v654
• Description: 2.25v To 3.6v Quad Uart With 64-byte Fifo
• Manufacturer: Exar Corporation

XR16V654/654D
2.25V TO 3.6V QUAD UART WITH 64-BYTE FIFO
SEE”RECEIVER” ON PAGE 19.
SEE”TRANSMITTER” ON PAGE 17.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
A
4.3.1
A2-A0
X X X
DDRESS
0 1 0
1 0 0
1 0 1
1 1 0
1 1 1
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
T
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
ABLE
IER versus Receive FIFO Interrupt Mode Operation
XOFF1 RD/WR
XOFF2 RD/WR
FSTAT
XON1 RD/WR
XON2 RD/WR
N
EFR
R
AME
EG
10: INTERNAL REGISTERS DESCRIPTION.
RD/WR
R
W
RD
EAD
RITE
/
RDYD#
Enable
CTS#
B
Auto
Bit-7
Bit-7
Bit-7
Bit-7
RX-
IT
-7
RDYC#
Enable
RTS#
B
Auto
Bit-6
Bit-6
Bit-6
Bit-6
RX-
IT
-6
Enhanced Registers
Special
RDYB#
Select
B
Char
Bit-5
Bit-5
Bit-5
Bit-5
RX-
IT
-5
28
MCR[7:5],
FCR[5:4],
IER [7:4],
ISR [5:4],
RDYA#
Enable
B
DLD
Bit-4
Bit-4
Bit-4
Bit-4
RX-
IT
-4
S
HADED BITS ARE ENABLED WHEN
RDYD#
B
ware
Flow
Soft-
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Cntl
TX-
IT
-3
RDYC#
B
ware
Soft-
Flow
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Cntl
TX-
IT
-2
RDYB#
B
Soft-
ware
Flow
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Cntl
TX-
IT
-1
EFR B
RDYA#
B
Soft-
ware
Flow
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Cntl
TX-
IT
-0
IT
-4=1
address lines
FSRS# pin is
a logic 0. No
LCR=0
C
REV. 1.0.1
required.
OMMENT
X
BF