xr16v794iv Exar Corporation, xr16v794iv Datasheet - Page 8

• Manufacturer Part Number: xr16v794iv
• Description: High Performance 2.25v To 3.6v Quad Uart With Fractional
• Manufacturer: Exar Corporation

XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to
obtain a 16X or 8X sampling clock of the serial data rate. The sampling clock is used by the transmitter for data
bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the value
of ’1’ (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed during
initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and
the DLD register provides the fractional part of the dvisior. Only the four lower bits of the DLD are implemented
and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming
the Baud Rate Generator Registers DLL, DLM and DLD provides the capability for selecting the operating data
rate.
If the pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in
8X sampling rate, these data rates would double. Also, when using 8X sampling mode, please note that the bit-
time will have a jitter (+/- 1/16) whenever the DLD is non-zero and is an odd number. When using a non-
standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s):
The closest divisor that is obtainable in the 794 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
F
2.6
IGURE
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
Required Divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16),
Required Divisor (decimal) = (XTAL1 clock frequency / prescaler / (serial data rate x 8),
Table 4
4. B
Programmable Baud Rate Generator with Fractional Divisor
AUD
shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate.
XTAL1
XTAL2
R
ATE
G
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
ENERATOR
Crystal
Buffer
Osc/
DLL = TRUNC(Required Divisor) & 0xFF
Channels
To Other
DLM = TRUNC(Required Divisor) >> 8
Divide by 4
Divide by 1
Prescaler
Prescaler
8
MCR Bit-7=0
MCR Bit-7=1
(default)
DLL, DLM and DLD
Fractional Baud
Rate Generator
Registers
Logic
WITH
to Transmitter
and Receiver
WITH
Rate Clock
16X or 8X
Sampling
8XMODE [7:0]
8XMODE [7:0]
Table 4
IS
REV. 1.0.0
IS
1
0
. At