xr16l2752ij Exar Corporation, xr16l2752ij Datasheet
xr16l2752ij
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xr16l2752ij Summary of contents
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MAY 2005 GENERAL DESCRIPTION 1 The XR16L2752 (2752 low voltage dual universal asynchronous receiver and transmitter (UART) with 5 Volt tolerant inputs. The device operates from 2.25 to 5.5 Volt supply range and is pin-to-pin compatible to ...
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... XTAL1 11 GND 12 XTAL2 CHSEL 16 INTB 17 ORDERING INFORMATION ART UMBER XR16L2752CJ 44-Lead PLCC XR16L2752IJ 44-Lead PLCC XR16L2752 44-pin PLCC O T ACKAGE PERATING EMPERATURE 0°C to +70°C -40°C to +85° REV. 1.2.1 39 RXA 38 TXA 37 DTRA# 36 RTSA# 35 MFA# 34 INTA ...
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REV. 1.2.1 PIN DESCRIPTIONS Pin Description 44-PLCC N T AME YPE DATA BUS INTERFACE Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO Pin Description 44-PLCC N T AME YPE RXA 39 I UART channel A Receive Data or infrared receive data. Normal receive data input must idle HIGH. The infrared receiver ...
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REV. 1.2.1 Pin Description 44-PLCC N T AME YPE CTSB UART channel B Clear-to-Send (active low) or general purpose input. It can be used for auto CTS flow control, see EFR[7], and IER[7]. This ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 1.0 PRODUCT DESCRIPTION The XR16L2752 (2752) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device configuration registers. ...
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REV. 1.2.1 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 2752 data interface supports the Intel compatible ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO CS 2.6 Channel A and B Internal Registers Each UART channel in the 2752 has a set of enhanced registers for control, monitoring and data loading and unloading. The ...
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REV. 1.2.1 2.9 INTA and INTB Outputs The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup. Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see through ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency tolerance) connected externally between ...
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REV. 1.2.1 divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16XMode [EMSR bit- divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8), with 16XMode [EMSR ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO IGURE RANSMITTER PERATION IN NON Data Byte 16X or 8X Clock (EMSR bit-7) 2.12.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with up ...
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REV. 1.2.1 when data is not received for 4 word lengths as defined by LCR[1,0] plus 12 bits time. This is equivalent to 3.7- 4.6 character times. The RHR interrupt is enabled by IER bit-0. 2.13.1 Receive Holding Register ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 2.14 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to ...
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REV. 1.2.1 F 11. A RTS CTS F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# TXB Data Starts RXA ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 2.17 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the 2752 will ...
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REV. 1.2.1 2.20 Infrared Mode The 2752 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/ bit ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 2.21 Sleep Mode with Auto Wake-Up The 2752 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All ...
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REV. 1.2.1 2.22 Internal Loopback The 2752 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 13 ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 3.0 UART INTERNAL REGISTERS Each of the UART channel in the 2752 has its own set of configuration registers selected by address lines A0, A1 and A2 with CS# and CHSEL selecting ...
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REV. 1.2 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO T 8: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE DLL RD/WR Bit DLM RD/WR ...
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REV. 1.2.1 4.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT and receive interrupts (IER BIT are enabled, the RHR interrupts (see ISR bits 2 and 3) status will reflect ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the software flow control, receive Xoff interrupt. (default) • Logic 1 = Enable the software flow control, receive Xoff interrupt. ...
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REV. 1.2 ABLE P ISR R RIORITY EGISTER EVEL ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO FCR[2]: TX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic transmit FIFO reset (default). • Logic 1 = Reset the transmit FIFO ...
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REV. 1.2.1 T 10: T ABLE RANSMIT AND T FCTR FCTR FCR RIGGER ABLE Table Table Table-C ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT-2 LCR[3]: TX and RX Parity Select Parity ...
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REV. 1.2.1 LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space”, LOW state). This condition remains, until disabled by setting LCR bit-6 to ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO MCR[1]: RTS# Output The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by EFR bit-6. If the modem interface is not used, ...
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REV. 1.2.1 LSR[2]: Receive Data Parity Error Flag • Logic parity error (default). • Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect. This error is ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO MSR[3]: Delta CD# Input Flag • Logic change on CD# input (default). • Logic 1 = Indicates that the CD# input has changed state since the last time it ...
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REV. 1.2.1 EMSR[5:4]: Extended RTS Hysteresis EMSR EMSR[6]: LSR Interrupt Mode • Logic 0 = LSR Interrupt Delayed (for 16C2550 ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 4.14 Baud Rate Generator Registers (DLL and DLM) - Read/Write The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the baud rate: ...
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REV. 1.2.1 FCTR[5:4]: Transmit/Receive Trigger Table Select See Table 10. FCTR FCTR[6]: Scratchpad Swap • Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode. • ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO T ABLE EFR -3 EFR -2 BIT BIT ONT ONT ...
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REV. 1.2.1 EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when the receive FIFO is ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO T 16: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLM and DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up. They ...
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REV. 1.2.1 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (44-PLCC) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED S ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED LOAD WHERE APPLICABLE S P YMBOL ARAMETER - Crystal Frequency CLK External Clock Low/High Time OSC External Clock Frequency ...
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REV. 1.2.1 AC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED LOAD WHERE APPLICABLE S P YMBOL ARAMETER T Reset Pulse Width RST N Baud Rate Divisor Bclk Baud Clock F 14 IGURE ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO F 16 IGURE ATA US EAD IMING A0-A2 Valid Address T AS CSA#/ CSB# IOR# T RDV D0- IGURE ATA US RITE ...
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REV. 1.2 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 (Unloading) Bit ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO F 20 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX D0:D7 D0: Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# (Reading ...
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REV. 1.2 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* Data in TX FIFO TXRDY IOW# (Loading data into FIFO) ...
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XR16L2752 2.25V TO 5.5V DUART WITH 64-BYTE FIFO PACKAGE DIMENSIONS (44 PIN PLCC Note: The control dimension is the millimeter column SYMBOL ...
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... Updated the Data Access Time (T reset state of MCR bit-3 in MFA# and MFB# pin descriptions. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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XR16L2752 REV. 1.2.1 GENERAL DESCRIPTION .................................................................................................1 A ................................................................................................................................................1 PPLICATIONS F .....................................................................................................................................................1 EATURES F 1. XR16L2752 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT .................................................................................................................................2 ORDERING INFORMATION PIN DESCRIPTIONS .........................................................................................................3 1.0 PRODUCT DESCRIPTION ...
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TO 5.5V DUART WITH 64-BYTE FIFO 4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 23 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 23 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 24 4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... ...