xr16c850im Exar Corporation, xr16c850im Datasheet - Page 3

• Manufacturer Part Number: xr16c850im
• Description: Uart With 128-byte Fifos And Infrared Irda Encoder/decoder
• Manufacturer: Exar Corporation

ORDERING INFORMATION
xr
REV. 2.3.1
PIN DESCRIPTIONS
N
I
NTEL
OTE
N
IOW#
IOR#
IOW
IOR
D0
D1
D2
D3
D4
D5
D6
D7
: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
A2
A1
A0
AME
XR16C850CM
B
P
XR16C850CJ
XR16C850IM
XR16C850IJ
ART
US
M
N
ODE
UMBER
44-P
PLCC
29
30
31
24
25
20
21
2
3
4
5
6
7
8
9
I
IN
NTERFACE
48-P
TQFP
26
27
28
43
44
45
46
47
19
20
16
17
3
4
2
IN
. T
T
I/O
YPE
HE
I
I
I
I
I
44-Lead PLCC
48-Lead TQFP
44-Lead PLCC
48-Lead TQFP
SEL
P
Address data lines [2:0]. A2:A0 selects internal UART’s configuration registers.
Data bus lines [7:0] (bidirectional).
Input/Output Read (active low). The falling edge instigates an internal read cycle
and retrieves the data byte from an internal register pointed by the address lines
[A2:A0], places it on the data bus to allow the host processor to read it on the lead-
ing edge. Either an active IOR# or IOR is required to transfer data from 850 to CPU
during a read operation. If not used, connect this pin to VCC. Caution:
TORY TEST MODE” ON PAGE 7.
Input/Output Read (active high). Same as IOR# but active high. Either an active
IOR# or IOR is required to transfer data from 850 to CPU during a read operation.
If not used, connect this pin to GND. During PC Mode, this pin becomes A3. Cau-
tion:
Input/Output Write (active low). The falling edge instigates the internal write cycle
and the rising edge transfers the data byte on the data bus to an internal register
pointed by the address lines [A2:A0]. Either an active IOW# or IOW is required to
transfer data from 850 to the Intel type CPU during a write operation. If not used,
connect this pin to VCC. Caution:
Input/Output Write (active high). The rising edge instigates the internal write cycle
and the falling edge transfers the data byte on the data bus to an internal register
pointed by the address lines [A2:A0]. Either an active IOW# or IOW is required to
transfer data from 850 to the Intel type CPU during a write operation. During PC
Mode, this pin becomes A8. If not used, connect this pin to GND. Caution:
SEE”FACTORY TEST MODE” ON PAGE 7.
ACKAGE
PIN IS CONNECTED TO
SEE”FACTORY TEST MODE” ON PAGE 7.
3
O
PERATING
VCC.
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
2.97V TO 5.5V UART WITH 128-BYTE FIFO
R
ANGE
SEE”FACTORY TEST MODE” ON PAGE 7.
T
D
EMPERATURE
ESCRIPTION
D
EVICE
Active
Active
Active
Active
S
TATUS
XR16C850
SEE”FAC-