xr16c850im Exar Corporation, xr16c850im Datasheet - Page 5

• Manufacturer Part Number: xr16c850im
• Description: Uart With 128-byte Fifos And Infrared Irda Encoder/decoder
• Manufacturer: Exar Corporation

xr
REV. 2.3.1
PC M
BAUD-
DDIS#
LPT1#
OUT#
N
OP2#
AEN#
IRQA
IRQB
IRQC
A3
A4
A5
A6
A7
A8
A9
S1
S2
S3
AME
ODE
I
NTERFACE
44-P
PLCC
17
26
35
25
12
14
15
16
21
28
23
10
35
33
32
27
17
1
IN
48-P
S
TQFP
IGNALS
12
22
31
20
10
17
37
24
21
31
30
29
23
12
11
6
9
5
IN
T
. C
YPE
O
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I
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ONNECT
Baud Rate Generator Output (active low). This pin provides the 16X clock of the
selected data rate from the baud rate generator. The RCLK pin must be connected
externally to BAUDOUT# when the receiver is operating at the same data rate.
When the PC mode is selected, the baud rate generator clock output is internally
connected to the RCLK input. This pin then functions as the printer port decode
logic output (LPT1#), see
Drive Disable Output. This pin goes to a logic 0 whenever the host CPU is reading
data from the 850. It can control the direction of a data bus transceiver between the
CPU and 850 or other logic functions. If 16 bit bus mode is selected, this pin
becomes D12. During PC Mode, this pin becomes LPT2#.
Output Port 2. General purpose output. During PC Mode, this pin becomes S3.
Address-3 Select Bit. This pin is used as the 4th address line to decode the
COM1-4 and LPT ports. See
becomes IOR.
Address-4 Select Bit. This pin is used as the 5th address line to decode the
COM1-4 and LPT ports. This pin has an internal 100kΩ pull-up resistor. This pin is
not available on the 40-Pin PDIP package which operates in the Intel Bus Mode
Only. See
Address-5 thru Address-8 Select Bit. These pins are used as the 6th thru 9th
address lines to decode the COM1-4 and LPT ports. See
ing Intel Bus Mode, A5 becomes CS0, A6 becomes CS1, A7 becomes CS2#, and
A8 becomes IOW.
Address-9 Select Bit. This pin is used as the 10th address line to decode the
COM1-4 and LPT ports. This pin has an internal 100kΩ pull-up resistor. This pin is
not available on the 40-Pin PDIP package which operates in the Intel Bus Mode
Only. See
Address Enable input (active low). When AEN# transitions to logic 0, it decodes
and validates COM 1-4 ports address per S1, S2 and S3 inputs. During Intel Bus
Mode, this pin becomes AS#.
Select 1 to 3. These are the standard PC COM 1-4 ports and IRQ selection inputs.
See
resistor. This pin is not available on the 40 pin PDIP packages which operates in
the Intel Bus Mode Only. During Intel Bus Mode, S1 is inactive, S2 becomes
RCLK, and S3 becomes OP2#.
Interrupt Request A, B and C Outputs (active high, three-state). These are the
interrupt outputs associated with COM 1-4 to be connected to the host data bus.
See interrupt section for details. The Interrupt Requests A, B or C functions as
IRQx to the PC bus. IRQx is enabled by setting MCR bit-3 to logic 1 and the
desired interrupt(s) in the interrupt enable register (IER). During Intel Bus Mode,
IRQA becomes INT, IRQB becomes RXRDY#, and IRQC becomes TXRDY#.
Line Printer Port-1 Decode Logic Output (active low). This pin functions as the PC
standard LPT-1 printer port address decode logic output, see
rate generator clock output, BAUDOUT#, is internally connected to the RCLK input
in the PC mode. During Intel Bus Mode, LPT1# becomes BAUDOUT#.
Table 1
SEL
Table 1
Table 1
PIN TO
and
Table 3
GND
for details. During Intel Bus Mode, this pin is inactive.
for details. During Intel Bus Mode, this pin is inactive.
5
TO SELECT
Table 3
for details. The S1 pin has an internal 100kΩ pull-up
Table 1
2.97V TO 5.5V UART WITH 128-BYTE FIFO
.
D
ESCRIPTION
PC M
for details. During Intel Bus Mode, this pin
ODE
.
Table 1
Table 1
for details. Dur-
XR16C850
. The baud