xr88c681 Exar Corporation, xr88c681 Datasheet - Page 32
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xr88c681
Manufacturer Part Number
xr88c681
Description
Cmos Dual Channel Uart Duart
Manufacturer
Exar Corporation
Datasheet
1.XR88C681.pdf
(101 pages)
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The DUART’s
Figure 9, because its use will be addressed in Figure 10
and Figure 11.
8085 CPU Module Interrupt Structure
The 8085 CPU supports both Direct and “External”
Vectored Interrupt processing. The 8085 has 4 maskable
interrupt request inputs (RST 5.5, RST 6.5, RTS 7.5, and
INTR), and 1 non-maskable interrupt request input
Rev. 2.11
Figure 9. Schematic of the XR88C681 Interface to the 8085 CPU Module (Memory Mapped).
-
INTR pin was deliberately omitted from
TRAP
X1
RST 7.5
RST 6.5
INTR
-
X2
RST 5.5
8085 CPU
INTA
AD0 - AD7
A8 - A15
-
IO/M
-
ALE
-
WR
RD
1D - 8D
C
74LS373
1Q - 8Q
-
-MEMW
MEMR
32
(TRAP). When discussing interfacing for the interrupt
servicing of peripheral devices such as the DUART, we
are only concerned with the maskable interrupt request
inputs. Of the four maskable interrupt request inputs;
three of these inputs support “Direct Interrupt”
processing.
supports “External Vectored Interrupt” processing.
Table 11 lists these Interrupt Request inputs and their
characteristics/features.
A8 - A15
A4 - A7
Address
Decoder
A0 - A3
The remaining one interrupt request
-CS_DUART
-CS_OTHER_IC
A0 - A3
-
XR88C681
D0 - D7
-
-
CS
RD
WR